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Non-Memory-Mapped Registers
INTERRUPT FORCE BITS
IRQ2
SPORT0 Transmit
SPORT0 Receive
DAC Transmit
ADC Receive
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written with zeros.
Control/Status Registers
9
8
0
0
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
15
14
13
12
11
0
0
0
0
0
IMASK
7
6
5
4
3
0
0
0
0
0
IFC (write-only)
10
9
8
7
6
5
0
0
0
0
0
0
2
1
0
INTERRUPT ENABLES
0
0
0
1 = enable
0 = disable (mask)
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
ADC Receive
DAC Transmit
4
3
2
1
0
0
0
0
0
0
E
ADSP-21msp5x
ADSP-21msp5x
INTERRUPT CLEAR BITS
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
ADC Receive
DAC Transmit
SPORT0 Receive
SPORT0 Transmit
IRQ2
E – 19
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