Interrupt-Driven Operation; Hdr Overwrite Mode - Analog Devices adsp-2100 Manual

Host Interface Port
two consecutive reads—the second read will generate the correct status information (the
first read generates the previous status).
In Figure 7.3, host status synchronization is based on a pseudo-clock HCLK,
internal to the ADSP-21xx, which is a logical combination of HRD, HWR and HSEL.
The first event shown in the figure is a status change at d1. The host status will
then be updated after the HCLK low, HCLK high, HCLK low sequence at point
c1. A status change at d2 would wait for the HCLK low, HCLK high, HCLK low
sequence, and then host status would be updated at point c2.
Status synchronization for the ADSP-21xx requires one full CLKOUT cycle
(starting at the rising edge) after a status change. As shown in Figure 7.4, a status
change at point d1 would cause a 21xx HIP status update at c1. A status change
at d2 would cause a 21xx HIP status update at c2.
7.4.2

Interrupt-Driven Operation

Using an interrupt-driven protocol frees the host and the ADSP-21xx from
polling the HSR(s) to see when data is ready to be read. For interrupt-driven
transfers to the ADSP-21xx, the host writes data into an HDR, and the HIP
automatically generates an internal interrupt. The interrupt is serviced like any
other interrupt.
For transfers to the host, the ADSP-21xx writes data to an HDR, then sets a flag
output, which is connected to a host interrupt input, to signal the host that new
data is ready to be transferred. Flag outputs are discussed in detail in Chapter 9,
"System Interface." If the ADSP-21xx passes data to the host through only one
HDR, then that HDR can be read directly by the host when it receives the
interrupt. If more than one HDR is used to pass data, then the host must read
the appropriate HSR(s) to determine which HDR was written by the ADSP-21xx.
7.4.3

HDR Overwrite Mode

In most cases, the ADSP-21xx reads host data sent through the HIP faster than
the host can send them. However, if the host is sufficiently fast, if the ADSP-21xx
is busy, or if the ADSP-21xx is driven by a slow clock, there may be a delay in
servicing a host write interrupt. If the host computer uses a handshaking
protocol requiring the ADSP-21xx to assert HACK to complete a host transfer, the
ADSP-21xx can optionally hold off the next host write until it has processed the
current one.
If the HDR overwrite bit (bit 7 in HSR7) is cleared, and if the host tries to write to
a register before it has been read by the ADSP-21xx, HACK is not asserted until
the ADSP-21xx has read the previously written data. The host processor must
wait for HACK to be asserted. As described earlier, however, there is a delay from
when the host writes data to when the status is synchronized to the ADSP-21xx.
During this interval, it is possible for the host to write an HDR a second time
even when the overwrite bit is cleared.
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