Analog Devices adsp-2100 Manual page 163

Host Interface Port
2. The host waits at least two ADSP-21xx processor cycles.
3. Starting with the instruction which is to be loaded into the highest
address of internal program memory, the host writes an instruction
into HDR0, HDR2 and HDR1 (in that order), one byte each. The upper
byte goes into HDR0, the lower byte goes into HDR2 and the middle
byte goes into HDR1.
4. The address of the instruction is decremented, and Step 3 is repeated.
This continues until the last instruction has been loaded into the HIP.
The ADSP-21xx reads the length of the boot load first, then bytes are
loaded from the highest address downwards. This results in shorter
booting times for shorter loads.
The number of instructions booted must be a multiple of eight. The boot
length value is given as:
length = (number of 24-bit program memory words ÷ 8) – 1
That is, a length of 0 causes the HIP to load eight 24-bit words.
In most cases, no handshaking is necessary, and the host can transfer data
at the maximum rate it is capable of. If the host operates faster than the
ADSP-21xx, wait states or NOPs must be added to the host cycle to slow it
down to one write every ADSP-21xx clock cycle.
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