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The quotient bit generated on each execution of DIVS and DIVQ is the AQ
bit which is written to the ASTAT register at the end of each cycle. The
final remainder produced by this algorithm (and left over in the AF
register) is not valid and must be corrected if it is needed. For more
information, consult the Division Exceptions appendix of this manual.
Status Generated:
ASTAT:
7
6
SS MV AQ AS
–
–
AQ
Loaded with the bit value equal to the AQ bit computed on each
cycle from execution of the DIVS or DIVQ instruction.
Instruction Format:
DIVQ, Instruction Type 23:
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
0
0
0
DIVS, Instruction Type 24:
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
0
0
0
5
4
3
AC AV AN AZ
*
–
–
1
1
1
0
0
0
1
1
0
0
0
0
2
1
0
–
–
–
1
0
Xop
0 0 0 0 0 0 0 0
Yop
Xop
0 0 0 0 0 0 0 0
ALU
15
DIVIDE
15 – 39
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