Serial Ports; Memory Interface & Sport Enables - Analog Devices adsp-2100 Manual

12.1.6

Serial Ports

SPORT0 and SPORT1 each have receive (RX), transmit (TX) and control
registers. The control registers are memory-mapped registers at locations
0x3FEF–0x3FFA in data memory. SPORT0 also has registers for
controlling its multichannel functions. Each SPORT control register
contains bits that control frame synchronization, companding, word
length and, in SPORT0, multichannel options. The SCLKDIV register for
each SPORT determines the frequency of the internally generated serial
clock, and the RFSDIV register determines the frequency of the internally
generated receive frame sync signal for each SPORT. The autobuffer
registers control autobuffering in each SPORT.
Programming a SPORT consists of writing its control register and,
depending on the modes selected, its SCLKDIV and/or RFSDIV registers
as well. The following example code programs SPORT0 for 8-bit µ-law
companding, normal framing, and an internally generated serial clock.
RFSDIV is set to 255, for 256 SCLK cycles between RFS assertions.
SCLKDIV is set to 2, resulting in an SCLK frequency that is 1/6 of the
CLKOUT frequency.
SI=0xB27;
DM(0X3FF6)=SI;
SI=2;
DM(0x3FF5)=SI;
SI=255;
DM(0x3FF4)=SI;
12.1.7 Memory Interface & SPORT Enables
The System Control Register, memory-mapped at DM(0x3FFF), contains
SPORT enables as well as the SPORT1 configuration selection. On all
ADSP-21xx processors except the ADSP-2181, it also contains fields for
controlling the booting operation: selecting the page, specifying the
number of wait states and forcing the boot in software. The System
Control Register also contains the PWAIT field which specifies the
number of wait states for external program memory accesses.
The Wait State Control Register, memory-mapped at data memory
location 0x3FFE, contains fields that specify the number of wait states for
each bank of data memory. On the ADSP-2181, it also specifies the number
of wait states for I/O memory space. In processors with optional on-chip
ROM, it also contains a bit for enabling the ROM.
Programming Model
{SPORT0 control register}
{SCLKDIV = 2}
{RFSDIV = 255}
12
12 – 7