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Control/Status Registers
Memory-Mapped Registers
SPORT0 Autobuffer Control Register
15
14
13
12
11
0
0
0
0
TIREG
BIASRND
MAC Biased Rounding Control Bit
(ADSP-2171, ADSP-2181, ADSP-21msp58/59 only)
CLKODIS
CLKOUT Disable Control Bit
(ADSP-2171, ADSP-2181, ADSP-21msp58/59 only)
Serial Clock Divide Modulus
15
14
13
12
11
Receive Frame Sync Divide Modulus
15
14
13
12
11
CLKOUT frequency
SCLKDIV =
2 * (SCLK frequency)
Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written with zeros.
10
9
8
7
6
TMREG
RIREG
SPORT0 SCLKDIV
10
9
8
7
6
SPORT0 RFSDIV
10
9
8
7
6
– 1
(Not on ADSP-2105)
5
4
3
2
1
0
RMREG
(Not on ADSP-2105)
5
4
3
2
1
5
4
3
2
1
SCLK frequency
RFSDIV =
RFS frequency
0
0
DM(0x3FF3)
RBUF
Receive Autobuffering Enable
TBUF
Transmit Autobuffering Enable
0
DM(0x3FF5)
0
DM(0x3FF4)
– 1
E
E – 5
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