Interrupts With Autobuffering Enabled; Unusual Complications - Analog Devices adsp-2100 Manual

5 Serial Ports
register with the expanded value. This can only occur on instruction cycle
boundaries and only one receive register can be expanded at a time. On
the ADSP-2100 family processors that have two serial ports (i.e. all except
the ADSP-2105), there is also a possibility of a delay due to the availability
of the companding circuitry. SPORT0 has the higher priority. When
companding is enabled, the autobuffer or interrupt request does not occur
until the register has been expanded. The next two diagrams show
examples of autobuffering with companding and the latencies involved.
The following diagram shows the latency when there are two pending
SCLK
DR
BIT3
DT
BIT3
Figure 5.40 Using One Index Register for Transmit and Receive Autobuffer
receive autobuffer requests with companding enabled.

5.13.10Interrupts With Autobuffering Enabled

When autobuffering is enabled, SPORT interrupts occur when the address
modification done during the autobuffer operation causes a modulus
wraparound. The synchronization delay applies to this type of interrupt as
well. An example is shown below in Figure 5.39:

5.13.11Unusual Complications

In most cases the serial port companding, autobuffer, and interrupt
latencies are transparent to your application program. When trying to use
the same I register for more than one autobuffer channel, it becomes
important to make sure that the latencies do not effect the correct order of
operations. For example, if the serial port data is continuous, and the
receiver and transmitter are working with the same frame signal, the order
of the transmit and receive autobuffer or interrupt operations may be
affected by the latencies shown below in Figure 5.40.
5 – 42
BIT2 BIT1 BIT0
BIT2 BIT1 BIT0
Transmit Autobuffer Request
Receive Autobuffer Request
BIT3 BIT2 BIT1
BIT3 BIT2 BIT1
BIT0
BIT0