Rom Program Memory Maps - Analog Devices adsp-2100 Manual

10 Memory Interface
ADSP-2101
ADSP-2111
ADSP-2171
ADSP-21msp58
0x0000
INTERNAL
RAM
2K
Loaded From
External
Boot Memory
0x07FF
0x0800
EXTERNAL
14K
0x3FFF
MMAP=0
Figure 10.4 Program Memory Maps (2K internal RAM)
Internal program memory RAM is fast enough to supply an instruction
and data in the same cycle, eliminating the need for cache memory.
Consequently, if the processor is operating entirely from on-chip memory,
it can fetch two operands and the next instruction on every cycle. It can
also fetch any one of these three from external memory with no
performance penalty.

10.2.3 ROM Program Memory Maps

The ADSP-2172 and ADSP-21msp59 processors contain mask-
programmable ROM on-chip. The program memory maps for these
processors are shown in Figures 10.6 and 10.7. The ADSP-2172 contains 8K
of ROM and the ADSP-21msp59 contains 4K.
On the ADSP-2172 and ADSP-21msp59, the ROM is enabled by setting the
ROMENABLE bit in the Data Memory Wait State control register (at
address DM[0x3FFE]). When the ROMENABLE bit is set to 1, addressing
program memory in the ROM range will access the on-chip ROM. When
ROMENABLE is set to 0, addressing program memory in this range will
access external program memory. The ROMENABLE bit is initialized to 0
after reset unless MMAP and BMODE=1.
10 – 6
0x0000
EXTERNAL
14K
0x37FF
0x3800
INTERNAL
RAM
2K
0x3FFF
MMAP=1
No Booting
ADSP-2105
ADSP-2115
0x0000
INTERNAL RAM
1K
Loaded From
External
Boot Memory
0x03FF
0x0400
Reserved
1K
0x07FF
0x0800
EXTERNAL
14K
0x3FFF
MMAP=0
Figure 10.5 Program Memory Maps (1K internal RAM)
0x0000
EXTERNAL
14K
0x37FF
0x3800
INTERNAL RAM
1K
0x3BFF
0x3C00
Reserved
1K
0x3FFF
MMAP=1
No Booting