Sport Timing Considerations; Companding Delay; Clock Synchronization Delay; Startup Timing - Analog Devices adsp-2100 Manual

5 Serial Ports
Figure 5.29 Complete Multichannel Example
5.13

SPORT TIMING CONSIDERATIONS

The SPORTs support full duplex operation and are normally interrupt
driven. That is, whenever a SPORT transaction has completed, the
processor generates an internal interrupt. Under most operating
conditions, the actual timing of the SPORT interrupts is not critical. In
some sophisticated DSP systems, however, it is important to know the
timing of the interrupt relative to the operation of the serial port.

5.13.1 Companding Delay

Use of the companding circuit introduces latency in two ways. First,
compressing or expanding a data value takes a single processor cycle.
Second, SPORT0 has priority over SPORT1 if both require an expansion or
compression operation in the same cycle; in this case, SPORT1 must wait
one processor cycle. See the section on companding earlier in this chapter
for more details on companding.

5.13.2 Clock Synchronization Delay

Some SPORT timings depend on the processor clock. Other timings
depend on the serial clock (SCLK0 or SCLK1). These clocks are
asynchronous. There is a delay associated with synchronizing the serial
clock to the processor clock whether the serial clock is internally or
externally generated. This delay is different for the transmit and receive
interrupts, as explained in the following sections.
5.13.2.1

Startup Timing

When a serial port is enabled by a write to the System Control Register, it
takes two SCLK cycles before it is actually enabled. On the next (third)
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