Chapter 7 Host Interface Port; Overview - Analog Devices adsp-2100 Manual

Host Interface Port 7
7.1

OVERVIEW

The host interface port (HIP) of the ADSP-2111, ADSP-2171, and
ADSP-21msp58/59 is a parallel I/O port that allows these processors to be
used as memory-mapped peripherals of a host computer (i.e. slave DSP
processors). Examples of host computers include the Intel 8051, Motorola
68000 family, and even other ADSP-21xx processors.
The host interface port can be thought of as an area of dual-ported
memory, or mailbox registers, that allow communication between the host
and the processor core of the ADSP-21xx. The host addresses the HIP as a
segment of 8- or 16-bit words of memory. To the processor core, the HIP is
a group of eight data-memory-mapped registers.
Any number of ADSP-21xx processors can be used in parallel as memory-
mapped peripherals. Assigning a different address location to each one
allows the host to control them all.
The operating speed of the HIP is similar to that of the processor data bus.
A read or write operation can occur within a single instruction cycle.
Because the HIP is normally connected with devices that are much slower
(the 68000, for example, can take four cycles to perform a bus operation),
the data transfer rate is usually limited by the host computer.
The host interface port is completely asynchronous to the rest of the
ADSP-21xx's operations. The host can write data to or read data from the
HIP while the ADSP-21xx is operating at full speed. The HIP can be
configured for operation on an 8-bit or 16-bit data bus and for either a
multiplexed address/data bus or separate address and data buses.
The ADSP-2111, ADSP-2171, and ADSP-21msp58/59 support two types of
booting operations. One method boots from external memory (usually
EPROM) using the boot memory interface described in the "Memory
Interface" chapter. The other method uses the HIP to boot load a program
from the host computer. HIP booting is described at the end of this
chapter.
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