Idma Port Functional Description - Analog Devices adsp-2100 Manual

11 DMA Ports
11.3.2
The IDMA Port lets a host system directly access internal ADSP-2181
memory locations (but not the memory-mapped control registers). Figure
11.8 shows a flow chart of the most general case for IDMA transfers.
In the case shown in Figure 11.8, the host system starts an IDMA transfer
by checking the state of the
busy). When the IDMA port is ready, the host directs the ADSP-2181 (with
IS
the
IDMA address/data bus to the IDMA Control Register. (Note that the
latched address cannot be read back by the host.)
Next, the host (using the
(or writing) the DSP's internal memory until done. With each IDMA read
or write operation, the the ADSP-2181 automatically increments the IDMA
internal memory address. Note that the ADSP-2181 continues program
execution throughout the IDMA transfer operation, except during the
"stolen" cycle used to do the memory access.
The case shown in Figure 11.8 is not the only way to use the IDMA port.
Some variations on this scheme include:
• After completing an IDMA port read/write operation, the host could
change the IDMA internal memory address and start a new operation
from a different starting address.
• After latching an IDMA internal memory address, the host could stop
the operation and come back at a later time to proceed with the read/
write operation. The IDMA starting memory address remains in the
IDMA Control Register until the host or DSP changes it.
• The ADSP-2181 can also read and write the IDMA Control Register as
part of your program. This means that the host could just control read/
write operations and let the ADSP-2181 control the IDMA starting
memory address.
• Using the IDMA short read cycle (which does not wait for the data-ready
assertion of the
buffer for IDMA read transfers. For information on how this data buffer
would work, see "IDMA Port Short Read Cycle" below.
• For ADSP-2181 applications with a host processor or host ASIC that
does not use a data-ready or write-complete acknowledge, use the
IDMA short read/write cycles.
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IDMA Port Functional Description

and IAL lines) to latch the IDMA internal memory address from the
IACK
IACK
line to determine port status (ready/
IS IRD IS
and or and
signal), you could set up a single-location data
IWR
lines) begins reading