Interrupt And Autobuffer Synchronization - Analog Devices adsp-2100 Manual

5 Serial Ports
received. The interrupt request occurs on the rising edge of SCLK after a
word is received (see Figure 5.32) and indicates that new data in the RX
register can be read.
Companding causes a delay in the same manner as for transmitting.
However, the latency is transparent, as the receive interrupt is generated
after the expansion has taken place.
The LSB is received on the falling edge of SCLK. One processor cycle
elapses to allow synchronization to the processor clock. One processor
CLKOUT
Figure 5.34 Synchronization of Autobuffer or Interrupt Request to Processor
Clock
cycle later, the SPORT attempts to expand the data if companding is
enabled and the other serial port is not using the companding circuitry.
Companding latencies as discussed above occur prior to generation of a
receive interrupt. Servicing the receive interrupt is subject to the same
latencies as other interrupts.
5.13.6 Interrupt & Autobuffer Synchronization
The serial ports are treated as an asynchronous system to the processor,
even if the processor is providing the serial clock. Internal to the processor
is a circuit which synchronizes the autobuffer or interrupt requests to the
processor clock. Figure 5.34 shows the synchronization delay for the serial
ports, assuming the setup and hold times are met for the current processor
cycle. The setup and hold times for the serial port requests are the same as
shown on the data sheet for the IRQ2 signal. If the setup and hold times
are not met, there is an additional processor cycle of delay added.
As shown in Figure 5.34, there is a two-processor-cycle delay before the
autobuffer or interrupt request is acted on by the processor. The same
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Request
Setup Time
Hold Time
Processor Can
Service The
Request Here