Reset - Analog Devices adsp-2100 Manual

9 System Interface
Using a 1X or 1/2X frequency input clock with the phase-locked loop to
generate the various internal clocks imposes certain restrictions. The CLKIN
signal must be valid long enough to achieve phase lock before RESET can be
deasserted. Also, the clock frequency cannot be changed unless the processor
is in RESET. Refer to the processor data sheets for details.
9.3
RESET halts execution and causes a hardware reset of the processor. The
RESET signal must be asserted when the processor is powered up to assure
proper initialization.
Tables 9.2–9.7 show the RESET state of various registers, including the
processors' on-chip memory-mapped status/control registers. The values of
any registers not listed are undefined at reset. The contents of on-chip
memory are unchanged after RESET, except as shown in Tables 9.2–9.7 for
the data-memory-mapped control/status registers. The CLKOUT signal
continues to be generated by the processor during RESET, except when
disabled on the ADSP-2171, ADSP-2181, or ADSP-21msp58/59.
The contents of the computation unit (ALU, MAC, Shifter) and data address
generator (DAG1, DAG2) registers are undefined following RESET.
When RESET is released, the processor's booting operation takes place,
depending on the state of the processor's MMAP pin. Program booting is
described in Chapter 10, "Memory Interface."
For the ADSP-2111, ADSP-2171, and ADSP-21msp58/59 processors, which
include a host interface port, setting the software reset bit in the HSR7
register has the same affect as asserting RESET. This allows either the host
processor or the ADSP-21xx to initiate a reset under software control.
In a multiprocessing system with several processors, a synchronous RESET is
required.
9.4
FORCED REBOOTING
Software-forced reboots can be accomplished in several ways. A software-
forced reboot clears the context of the processor and initializes some
registers. A context clear clears the processor stacks and restart execution at
address 0x0000. Table 9.1 shows the different ways each processor can
perform a software reboot.
9 – 4

RESET

SOFTWARE-