Overview - Analog Devices adsp-2100 Manual

15 Instruction Set Reference
15.2

OVERVIEW

This chapter provides an overview and detailed reference for the
instruction set of the ADSP-2100 family of DSP microprocessors.
For information regarding the ADSP-2100 Family Development Software,
refer to the ADSP-2100 Family Assembler Tools & Simulator Manual,
ADSP-2100 Family C Tools Manual, and ADSP-2100 Family C Runtime
Library Manual. These manuals provide a complete guide to the
development software. The handbooks Digital Signal Processing
Applications Using The ADSP-2100 Family, Volume 1 and Volume 2 present
DSP applications programs with source code and discussion.
The instruction set is tailored to the computation-intensive algorithms
common in DSP applications. For example, sustained single-cycle
multiplication/accumulation operations are possible. The instruction set
provides full control of the processors' three computational units: the
ALU, MAC and Shifter. Arithmetic instructions can process single-
precision 16-bit operands directly; provisions for multiprecision
operations are available.
The high-level syntax of ADSP-2100 family source code is both readable
and efficient. Unlike many assembly languages, the ADSP-2100 family
instruction set uses an algebraic notation for arithmetic operations and for
data moves, resulting in highly readable source code. There is no
performance penalty for this; each program statement assembles into one
24-bit instruction which executes in a single cycle. There are no multicycle
instructions in the instruction set. (If memory access times require, or
contention for off-chip memory occurs, overhead cycles will be required,
but all instructions can otherwise execute in a single cycle.)
In addition to JUMP and CALL, the instruction set's control instructions
support conditional execution of most calculations and a DO UNTIL
looping instruction. Return from interrupt (RTI) and return from
subroutine (RTS) are also provided.
The IDLE instruction is provided for idling the processor until an
interrupt occurs. IDLE puts the processor into a low-power state while
waiting for interrupts.
Two addressing modes are supported for memory fetches. Direct
addressing uses immediate address values; indirect addressing uses the I
registers of the two data address generators (DAGs).
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