Software Reset; Hip Interrupts - Analog Devices adsp-2100 Manual

7 Host Interface Port
If the HDR overwrite bit is set, the previous value in the HDR is
overwritten and HACK is returned immediately. If the ADSP-21xx is
reading the register that is being overwritten, the result is unpredictable.
After reset, the HDR overwrite bit is set. If the host does not require an
acknowledge (HACK is not used), the HDR overwrite bit should be always
be set, because there is no way for the ADSP-21xx to prevent overwrite.
7.4.4

Software Reset

Writing a 1 to bit 6 of HSR7 causes software reset of the ADSP-21xx. If the
ADSP-21xx writes the software reset bit, the reset happens immediately.
Otherwise, the reset happens as soon as the write is synchronized to the
ADSP-21xx system clock. The internal software reset signal is held for five
ADSP-21xx clock cycles and then released.
7.5 HIP
INTERRUPTS
HIP interrupts can be masked using either the IMASK register or the
HMASK register. Bits in the IMASK register enable or disable all HIP read
interrupts or all HIP write interrupts. The HMASK register, on the other
hand, has bits for masking the generation of read and write interrupts for
individual HDRs. In order for a read or write of an HDR to cause an
interrupt, the HIP read or write interrupt must be enabled in IMASK, and
the read or write to the particular HDR must be enabled in HMASK.
HMASK is mapped to memory location 0x3FE8. IMASK is described in
Chapter 3, "Program Control."
A host write interrupt is generated whenever the host completes a write to
an HDR. A host read interrupt is generated when an HDR is ready to
receive data from the ADSP-21xx—this occurs when the host has read the
previous data, and also after reset, before the ADSP-21xx has written any
data to the HDR. HMASK, however masks all HIP interrupts at reset. The
read interrupt allows the ADSP-21xx to transfer data to the host at a high
rate without tying up the ADSP-21xx with polling overhead.
HMASK allows reads and writes of some HDRs to not generate interrupts.
For example, a system might use HDR2 and HDR1 for data values and
HDR0 for a command value. Host write interrupts from HDR2 and HDR1
would be masked off, but the write interrupt from HDR0 would be
unmasked, so that when the host wrote a command value, the ADSP-21xx
would process the command. In this way, the overhead of servicing
7 – 10