Next Address Select Logic - Analog Devices adsp-2100 Manual

Program Control 3
3.2.1

Next Address Select Logic

While the processor is executing an instruction, the program sequencer
pre-fetches the next instruction. The sequencer's next address select logic
generates a program memory address (for the pre-fetch) from one of four
sources:
• PC incrementer
• PC stack
• instruction register
• interrupt controller
The next address circuit (shown in Figure 3.1) selects which of these
sources is used, based on inputs from the instruction register, condition
logic, loop comparator and interrupt controller. The next instruction
address is then output on the PMA bus for the pre-fetch.
The PC incrementer is selected as the source of the next address if
program flow is sequential. This is also the case when a conditional jump
or return is not taken and when a DO UNTIL loop terminates. The output
of the PC incrementer is driven onto the PMA bus and is loaded back into
the program counter to begin the next cycle.
The PC stack is used as the source for the next address when a return from
subroutine or return from interrupt is executed. The top stack value is also
used as the next address when returning to the top of a DO UNTIL loop.
The instruction register provides the next address when a direct jump is
taken. The 14-bit jump address is embedded in the instruction word.
The interrupt controller provides the next program memory address when
servicing an interrupt. Upon recognizing a valid interrupt, the processor
jumps to the interrupt vector location corresponding to the active
interrupt request.
Another possible source for the next address is one of the I4-I7 index
registers of DAG2 (Data Address Generator 2), used when a register
indirect jump is executed as in the following instruction:
JUMP (I4);
In this case the program counter (PC) is loaded from DAG2 via the PMA
bus. (Data address generators are described in Chapter 4.)
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