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5 Serial Ports
31
30
15
14
1 = Channel Enabled
0 = Channel Ignored
31
30
15
14
word length is still set by the SLEN field in the SPORT control register and
can be 3 to 16 bits.
The multichannel frame delay (MFD) is a 4-bit field specifying (in binary)
the number of serial clock cycles between the frame sync signal and the
first data bit. This allows the processor to work with different types of T1
interface devices. Figure 5.26 shows a variety of delays.
Figure 5.26 SPORT Multichannel Frame Delay Examples
The memory-mapped receive enable register and transmit enable register
are each 32 bits wide and made up of two contiguous sixteen-bit registers,
as shown in Figure 5.27, which can be found on the next page. Each bit
corresponds to a channel; setting the bit enables that channel so that the
processor will select its word from the 24- or 32-word block. For example,
setting bit 0 selects word 0, bit 12 selects word 12, and so on.
Figure 5.27 SPORT0 Multichannel Word Enable Registers
5.12.2 Multichannel Operation
Received words for channels that are not enabled are ignored; that is, no
interrupts are generated for these words, no autobuffering occurs and no
data is written to the RX0 register. Likewise, there are no interrupts and
no autobuffering for transmit words that are not enabled. During transmit
word time slots for channels that are not enabled, the data transmit (DT)
pin is tristated.
Most aspects of SPORT0 operate normally in the multichannel mode.
Specifically, word length (SLEN), internal or external framing (IRFS),
5 – 32
29
28
27
26
25
24
13
12
11
10
9
8
29
28
27
26
25
24
13
12
11
10
9
8
23
22
21
20
19
18
7
6
5
4
3
2
23
22
21
20
19
18
7
6
5
4
3
2
17
16
0x3FFA
Receive
1
0
Word
Enables
0x3FF9
17
16
0x3FF8
Transmit
Word
1
0
Enables
0x3FF7
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