Chapter 6 Timer; Overview; Timer Architecture - Analog Devices adsp-2100 Manual

6.1

OVERVIEW

The programmable interval timer can generate periodic interrupts based
on multiples of the processor's cycle time. When enabled, a 16-bit count
register is decremented every n cycles, where n–1 is a scaling value stored
in an 8-bit register. When the value of the count register reaches zero, an
interrupt is generated and the count register is reloaded from a 16-bit
period register.
The scaling feature of the timer allows the 16-bit counter to generate
periodic interrupts over a wide range of periods. Given a processor cycle
time of 80 ns, the timer can generate interrupts with periods of 80 ns up to
5.24 ms with a zero scale value. When scaling is used, time periods can
range up to 1.34 seconds.
Timer interrupts can be masked, cleared and forced in software if desired.
For additional information, refer to the section "Interrupts" in Chapter 3,
"Program Control."
6.2

TIMER ARCHITECTURE

The timer includes two 16-bit registers, TCOUNT and TPERIOD and one
8-bit register, TSCALE. The extended mode control instruction enables
and disables the timer by setting and clearing bit 5 in the mode status
register, MSTAT. For a description of the mode control instructions, refer
to Chapter 15, Instruction Set Reference. The timer registers, which are
memory-mapped, are shown in Figure 6.1 (on the following page).
TCOUNT is the count register. When the timer is enabled, it is
decremented as often as once every instruction cycle. When the counter
reaches zero, an interrupt is generated. TCOUNT is then reloaded from
the TPERIOD register and the count begins again.
Timer 6
6 – 1