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Non-Memory-Mapped Registers
INTERRUPT FORCE BITS
SPORT0 Transmit
(must be set to 0 for ADSP-2105)
SPORT0 Receive
(must be set to 0 for ADSP-2105)
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written with zeros.
Control/Status Registers
5
0
11
10
9
0
0
0
IRQ2
Timer
IMASK
4
3
2
1
0
0
0
0
0
0
SPORT0 Transmit (must be set to 0 for ADSP-2105)
IFC (write-only)
8
7
6
5
4
3
0
0
0
0
0
0
INTERRUPT ENABLES
1 = enable
0 = disable (mask)
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
SPORT0 Receive (must be set to 0 for ADSP-2105)
IRQ2
2
1
0
0
0
0
INTERRUPT CLEAR BITS
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
SPORT0 Receive
(must be set to 0 for ADSP-2105)
SPORT0 Transmit
(must be set to 0 for ADSP-2105)
IRQ2
E
ADSP-2101
ADSP-2105
ADSP-2115
ADSP-2101
ADSP-2105
ADSP-2115
ADSP-2111
E – 15
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