Polled Operation - Analog Devices adsp-2100 Manual

Host Interface Port
Because the HIP typically communicates with a host computer that has
both a slower instruction rate and a multicycle bus cycle, the host
computer is usually the limiting factor in the speed of HIP transfers.
During a transfer, the ADSP-21xx executes instructions normally,
independent of HIP operation. This is true even during a multicycle
transfer from the host.
For host computers that require handshaking, the ADSP-21xx returns
HACK in the same cycle as the host access, except in overwrite mode. In
overwrite mode, the ADSP-21xx can extend a host access by not asserting
the HACK acknowledge until the cycle is complete. The user can enable
and disable overwrite mode by setting and clearing a bit in HSR7.
Overwrite mode is described in more detail later in this chapter.
The HDRs are not initialized during either hardware or software reset.
The host can write information to the HDRs before a reset, and the ADSP-
21xx can read this information after the reset is finished. During reset,
however, HIP transfers cannot occur; the HACK pin is deasserted and the
data pins are tristated.
Because a host computer that requires handshaking must wait for an
acknowledgement from the ADSP-21xx, it is possible to cause such a host
to hang. If, when the host has initiated a transfer, but has not yet received
an acknowledgement, the ADSP-21xx is reset, then the acknowledgement
can not be generated, thus causing the host to wait indefinitely.
There is no hardware in the HIP to prevent the host from writing a
register that the ADSP-21xx core is reading (or vice versa). If the host and
the ADSP-21xx try to write the same register at the same time, the host
takes precedence. Simultaneous writes should be avoided, however: since
the ADSP-21xx and the host operate asynchronously, simultaneous writes
can cause unpredictable results.
7.4.1

Polled Operation

Polling is one method of transferring data between the host and the
ADSP-21xx. Every time the host writes to an HDR, a bit is automatically
set in the lower byte of HSR6. This bit remains set until the ADSP-21xx
reads the HDR. Similarly, when the ADSP-21xx writes to an HDR, a bit in
the upper byte of HSR6 (and the lower byte of HSR7) is set. This bit is
cleared automatically when the host reads the HDR.
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