Long Write Cycle - Analog Devices adsp-2100 Manual

IACK
IS
IRD
IAD15-0
Figure 11.11 IDMA Short Read Cycle Timing

11.3.4.4 Long Write Cycle

The host writes the contents of an internal memory location using the
IDMA long write cycle. The write cycle, shown in Figure 11.12, consists of
the following steps:
1. Host ensures that
IWR
2. Host asserts
data on the IAD15-0 address/data bus to the location pointed to by the
target IDMA address .
3. ADSP-2181 deasserts the
write operation.
4. Host drives the data on the IAD address/data bus.
5. ADSP-2181 asserts
IAD15-0 address/data bus.
6. Host recognizes the
the IDMA address/data bus and deasserts
IDMA Long Write Cycle).
Note that IAL is low (inactive) and
write operation.
PREVIOUS
DATA
IACK
line is low.
IS
and (low), directing the ADSP-2181 to write the
IACK
line, indicating it recognizes the IDMA
IACK
line, indicating it latched the data on the
IACK
line is now low, stops driving the data on
IRD
DMA Ports
IWR IS
and
is high (inactive) throughout the
(ending the
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