Arithmetic Shift Immediate - Analog Devices adsp-2100 Manual

SHIFTER
15

ARITHMETIC SHIFT IMMEDIATE

Syntax:
Permissible xops
SI
SR1
SR0
AR
Example:
Description:
and direction specified by the constant in the exponent field. Positive
constants cause a left shift (upshift) and negative constants cause a right
shift (downshift). A positive constant must be entered without a "+" sign.
The shift may be referenced to the upper half of the output field (HI
option) or to the lower half (LO option). The shift output may be logically
ORed with the present contents of the SR register by selecting the SR OR
option.
For ASHIFT with a positive shift constant the operand is shifted left; with
a negative shift constant the operand is shifted right. The 32-bit output
field is sign-extended to the left (the MSB of the input is replicated to the
left), and the output is zero-filled from the right. Bits shifted out of the
high order bit in the 32-bit destination field (SR
out of the low order bit in the destination field (SR
To shift a double precision number, the same shift constant is used for
both halves of the number. On the first cycle, the upper half of the number
is shifted using an ASHIFT with the HI option; on the following cycle, the
lower half is shifted using an LSHIFT with the LO and OR options. This
prevents sign bit extension of the lower word's MSB.
* See Table 2.4 in Chapter 2.
Status Generated:
15 – 60
SR = [SR OR] ASHIFT xop BY <exp>
<exp>
MR0 Any constant between –128 and 127*
MR1
MR2
SR = SR OR ASHIFT SR0 BY 3 (LO);
Arithmetically shift the bits of the operand by the amount
None affected.
(HI)
(LO)
{do not use "+3"}
) are dropped. Bits shifted
31
) are dropped.
0
;