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7 Host Interface Port
7.2
SUMMARY
The HIP consists of 27 pins. As shown in Table 7.1, 16 of these are data
pins and 11 are control pins. Some of the control pins have dual functions,
allowing the processor to support different bus protocols.
Pin
Name
HSEL
HACK
HSIZE
BMODE
HMD0
HRD/HRW
*
HWR/HDS
HMD1
HD15-0/HAD15-0
HA2 /ALE
HA1-0/no function
TOTAL
* HMD0 selects function
** HMD1 selects function
Table 7.1 Host Interface Port Pins
7 – 2
Number
of Pins
Direction
1
Input
1
Output
1
Input
1
Input
1
Input
*
1
Input
1
Input
1
Input
**
16
Bidirectional
**
1
Input
**
2
Input
27
HIP PIN
Function
HIP Select
HIP Acknowledge
HIP 8/16 Bit Host
0=16-bit; 1=8-bit
HIP Boot Mode Select
0=normal (EPROM); 1=HIP
HIP Bus Strobe Select
0=RD, WR; 1=RW, DS
HIP Read Strobe/
Read/Write Select
HIP Write Strobe/
Host Data Strobe
HIP Address/Data Mode
0=separate; 1=multiplexed
HIP Data/Address & Data
HIP Host Address 2/
Address Latch Enable
Host Addresses 1 & 0
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