Program Sequencer; Interrupts; Loop Counts - Analog Devices adsp-2100 Manual

12 Programming Model
12.1.2

Program Sequencer

Registers associated with the program sequencer control subroutines,
loops, and interrupts. They also indicate status and select modes of
operation.

12.1.2.1 Interrupts

The ICNTL register controls interrupt nesting and external interrupt
sensitivity; the IFC register lets you force and clear interrupts in software;
the IMASK register masks (disables) individual interrupts. The widths of
the IFC and IMASK registers depend on the processor, since different
ADSP-21xx processors support different numbers of interrupts.
The ADSP-2171, ADSP-2181, and ADSP-21msp58/59 support a global
interrupt enable instruction (ENA INTS) and interrupt disable instruction
(DIS INTS).
Interrupts are enabled by default at reset. Executing the disable interrupt
instruction causes all interrupts to be masked without changing the
contents of the IMASK register. Disabling interrupts does not affect serial
port autobuffering, which will operate normally whether or not interrupts
are enabled. The disable interrupt instruction masks all user interrupts
including the powerdown interrupt.
The interrupt enable instruction allows all unmasked interrupts to be
serviced again.

12.1.2.2 Loop Counts

The CNTR register stores the count value for the currently executing loop.
The count stack allows the nesting of count-based loops to four levels. A
write to CNTR pushes the current value onto the count stack before
writing the new value. For example:
CNTR=10;
pushes the current value of CNTR on the count stack and then loads
CNTR with 10.
OWRCNTR is a special syntax with which you can overwrite the count
value for the current loop without pushing CNTR on the count stack.
OWRCNTR cannot be read (i.e. used as a source register), and must not be
written in the last instruction of a DO UNTIL loop.
12 – 4