Analog Devices adsp-2100 Manual page 416

Because of the read-first, write-second characteristic of the processor,
using the same register as source in one clause and a destination in the
other is legal. The register supplies the value present at the beginning of
the cycle and is written with the new value at the end of the cycle.
For example,
(1) AR = AX0 + AY0, AX0 = DM (I0, M0);
is a legal version of this multifunction instruction and is not flagged by the
assembler. Reversing the order of clauses, as in
(2) AX0 = DM (I0, M0) , AR = AX0 + AY0;
results in an assembler warning, but assembles and executes exactly as the
first form of the instruction. Note that reading example (2) from left to
right may suggest that the data memory value is loaded into AX0 and
then used in the computation, all in the same cycle. In fact, this is not
possible. The left-to-right logic of example (1) suggests the operation of
the instruction more closely. Regardless of the apparent logic of reading
the instruction from left to right, the read-first, write-second operation of
the processor determines what actually happens.
Using the same register as a destination in both clauses, however,
produces an indeterminate result and should not be done. The assembler
issues a warning unless semantics checking is turned off. Regardless of
whether or not the warning is produced, however, this practice is not
supported.
The following, therefore, is illegal and not supported, even though
assembler semantics checking produces only a warning:
(3) AR = AX0 + AY0, AR = DM (I0, M0);
COMPUTATION with MEMORY READ
(instruction continues on next page)
MULTIFUNCTION
Illegal!
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