Analog Devices adsp-2100 Manual page 266

Host starts IDMA transfer.
Host checks IACK control line to
see if the DSP is "Busy".
Host uses IS and IAL control lines to
latch the DMA starting address
(IDMAA) and PM/DM selection into the
DSP's IDMA Control Register. The
DSP also can set the starting address
and memory destination.
Host uses IS and IRD (or IWR) to
read (or write) DSP internal memory
(PM or DM).
Host ends IDMA transfer.
Figure 11.8 General IDMA Transfer Flow Chart
There are some restrictions on IDMA operations. These hardware/
software design restrictions include:
• If your design has both the host and ADSP-2181 writing to the IDMA
Control Register, do not let both write to this register at the same time;
the results of this are indeterminate.
• Host reads of internal Program Memory take two IDMA reads (for a 24-
bit word through a 16-bit port). If an IDMA address latch cycle or a
ADSP-2181 write to the IDMA Control Register occurs after the first
Program Memory read cycle, the IDMA port "loses" the second half of
the 24-bit Program Memory word. The next IDMA read or write uses
the address selected by the new contents of the IDMA Control Register.
Note that writing to the IDMA Control Register after the first half of a
Program Memory IDMA read lets you read just 16-bit data from
Program Memory.
More?
Done?
DMA Ports
Continue
Host checks IACK line to see if the
DSP has completed the previous
IDMA operation.
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