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Control/Status Registers
E.1
OVERVIEW
This appendix shows bit definitions for 1) the memory-mapped control
registers and 2) other (non-memory-mapped) control and status registers
of all ADSP-21xx processors. The memory-mapped registers are listed in
descending address order. Default bit values at reset are shown; if no
value is shown, the bit is undefined at reset. Reserved bits are shown on a
gray field. These bits should always be written with zeros.
Memory-Mapped Registers
15
0
SPORT0 Enable
1 = enabled, 0 = disabled
(set to 0 for ADSP-2105)
SPORT1 Enable
1 = enabled, 0 = disabled
SPORT1 Configure
1 = serial port
0 = FI, FO, IRQ0, IRQ1, SCLK
System Control Register
14
13
12
11
10
0
0
0
0
1
BFORCE
Boot Force Bit
(not on ADSP-2181)
* Bit 5 initialized to 1 on ADSP-2171, ADSP-21msp58/59
Bit 5 initialized to 0 on ADSP-2101, ADSP-2105, ADSP-2115, ADSP-2111
9
8
7
6
5
0
0
0
0
*
BPAGE
Boot Page Select
(not on ADSP-2181)
4
3
2
1
0
1
1
1
1
1
PWAIT
Program Memory
Wait States
BWAIT
Boot Wait States*
(not on ADSP-2181)
E
DM(0x3FFF)
E – 1
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