Analog Devices adsp-2100 Manual page 157

Host Interface Port
15 14
0
Host HDR5 Read
Host HDR4 Read
Host HDR3 Read
Host HDR2 Read
Host HDR1 Read
Host HDR0 Read
Figure 7.5 HMASK Register
interrupts when the host writes data values is avoided.
The HMASK register is organized in the same way as HSR6; the mask bit is in
the same location as the status bit for the corresponding register. The lower byte
of HMASK masks host write interrupts and the upper byte masks host read
interrupts. The bits are all positive sense (0=masked, 1=enabled).
HMASK is mapped to the internal data memory space at location 0x3FE8. At
reset, the HMASK register is all zeros, which means that all HIP interrupts are
masked.
HIP read and write interrupts are not cleared by servicing such an interrupt.
Reading the HDR clears a write interrupt, and writing the HDR clears a read
interrupt. The logical combination of all read and write interrupt requests
generates a HIP interrupt. Pending interrupt requests remain until all HIP
interrupts are cleared by either reading or writing the appropriate HIP data
register. If the ADSP-21xx is reading registers that the host might be writing, it is
not certain that an interrupt will be generated. To ensure that all host writes
generate interrupts, you must make sure that the ADSP-21xx is not reading the
HDRs that the host is writing. While servicing the interrupt, the status register
can be read to determine which operation generated the interrupt and whether
multiple interrupt requests need to be serviced.
HIP interrupts cannot be forced or cleared by software, as other interrupts can.
The HIP write interrupt vector is location 0x0008. The HIP read interrupt vector
is location 0x000C.
HMASK
13 12 11 10 9 8
0 0 0 0 0 0 0
INTERRUPT ENABLES
1=enable
0=disable
7 6 5 4 3 2 1
0 0 0 0 0 0 0
7
0
0
0x3FE8
Host HDR0 Write
Host HDR1 Write
Host HDR2 Write
Host HDR3 Write
Host HDR4 Write
Host HDR5 Write
7 –
11