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E Control/Status Registers
Non-Memory-Mapped Registers
ASTAT
7
6
5
4
3
2
1
0
0
0
0
0
0
0
SS MV AQ AS AC AV AN AZ
MSTAT
6
5
4
3
2
1
0
0
0
0
0
0
0
0
E – 14
0
0
ALU Result Zero
ALU Result Negative
ALU Overflow
ALU Carry
ALU X Input Sign
ALU Quotient
MAC Overflow
Shifter Input Sign
Register Bank Select
0=primary, 1=secondary
Bit-Reverse Addressing Enable (DAG1)
ALU Overflow Latch Mode Enable
AR Saturation Mode Enable
MAC Result Placement
0=fractional, 1=integer
Timer Enable
Go Mode Enable
SSTAT
(read-only)
7
6
5
4
3
2
1
0
1
0
1
0
1
0
ICNTL
4
3
2
0
1
PC Stack Empty
PC Stack Overflow
Count Stack Empty
Count Stack Overflow
Status Stack Empty
Status Stack Overflow
Loop Stack Empty
Loop Stack Overflow
1
0
IRQ0 Sensitivity
IRQ1 Sensitivity
IRQ2 Sensitivity
Interrupt Nesting
1=enable
0=disable
1=edge
0=level
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