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E Control/Status Registers
Memory-Mapped Registers
Flag Out (read-only)
Internal Serial Clock Generation
Receive Frame Sync Required
Receive Frame Sync Width
Transmit Frame Sync Required
Transmit Frame Sync Width
Internal Transmit Frame Sync Enable
15
E – 6
15
14
13
12
0
0
0
ISCLK
RFSR
RFSW
TFSR
TFSW
ITFS
Serial Clock Divide Modulus
15
14
13
12
11
10
Receive Frame Sync Divide Modulus
14
13
12
11
10
CLKOUT frequency
SCLKDIV =
2 * (SCLK frequency)
SPORT1 Control Register
11
10
9
8
7
6
0
0
0
0
0
0
SPORT1 SCLKDIV
9
8
7
6
5
SPORT1 RFSDIV
9
8
7
6
5
– 1
RFSDIV =
5
4
3
2
1
0
0
0
0
0
0
0
SLEN (Serial Word Length – 1)
DTYPE Data Format
00=right justify, zero-fill unused MSBs
01=right justify, sign-extend into unused MSBs
10=compand using µ-law
11=compand using A-law
INVRFS
Invert Receive Frame Sync
INVTFS
Invert Transmit Frame Sync
IRFS
Internal Receive Frame Sync Enable
4
3
2
1
0
4
3
2
1
0
SCLK frequency
RFS frequency
DM(0x3FF2)
DM(0x3FF1)
DM(0x3FF0)
– 1
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