Internally Generated Frame Sync Timing - Analog Devices adsp-2100 Manual

SCLK cycle, the serial port becomes active, looking for a frame sync.
5.13.3 Internally Generarated Frame Sync Timing
When internally generated frame syncs are used, all that is necessary to
transmit data, from the programmer's point of view, is to move the data
into the appropriate TX register with an instruction such as:
TX0 = AX0;
Once data is written into the TX register, the processor generates a frame
sync after a synchronization delay. This delay in turn affects the timing of
the serial port transmit interrupt. The latency depends on five factors: the
frequency of the serial clock, whether or not companding is enabled,
whether or not there is contention for the companding circuit, whether the
current word has finished transmitting and the logic level of the SCLK
TX Written, SCLK High
TX Written
Processor Clock
Serial Clock
TFS OUTPUT
(Normal Framing)
TFS OUTPUT
(Alternate Framing)
TX Written, SCLK Low
TX Written
Processor Clock
Serial Clock
TFS OUTPUT
(Normal Framing)
TFS OUTPUT
(Alternate Framing)
Figure 5.30 Clock Synchronization
Serial Ports
(Alternate Framing)
High Low High
MSB Transmitted
(Alternate Framing)
High Low High
MSB Transmitted MSB Transmitted
(Normal Framing)
MSB Transmitted
(Normal Framing)
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