Pwdack Pin - Analog Devices adsp-2100 Manual

9.7.7

PWDACK Pin

The powerdown acknowledge pin (PWDACK) is an output that indicates
when the processor is powered down. This pin is driven high by the
processor when it has powered down and is driven low when the
processor has completed its powerup sequence. A low level on the
PWDACK pin also indicates that there is a valid CLKOUT signal and that
instruction execution has begun. Figure 9.7 shows an example of timing
for the powerdown and restart sequence.
The processor is executing code when the PWD pin is brought low. The
processor vectors to the powerdown interrupt vector and an IDLE
instruction is executed causing the processor to go into powerdown. The
CLKOUT and PWDACK signals are driven high by the processor. At this
point, the input clock pin is ignored. If the processor is put into the
powerdown mode via the powerdown force bit in the powerdown control
register, the result is the same as described above.
The input clock is started and the PWD pin is brought high. After the
necessary start-up cycles the processor brings the PWDACK output low,
begins driving the CLKOUT pin with a clock signal and begins to fetch the
instruction after the IDLE instruction. The processor then resumes normal
operation.
CLKIN
PWD
PWDACK
CLKOUT
RUN
Figure 9.7 Powerdown Timing Example
System Interface
PWRDWN
PENDING
EXECUTE IDLE
NOP WHILE FETCHING INSTRUCTION FOLLOWING IDLE
POWERED
START CLK
DOWN
FINISH IDLE
9
RUN
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