Analog Devices adsp-2100 Manual page 34

2 Computational Units
AX0
R-BUS
Figure 2.3 DIVS Operation
When dividing unsigned numbers, the DIVS operation is not used.
Instead, the AQ bit in the arithmetic status register (ASTAT) should be
initialized to zero by manually clearing it. The AQ bit indicates to the
following operations that the quotient should be assumed positive.
The second division primitive is the "divide-quotient" (DIVQ) instruction
which generates one bit of quotient at a time and is executed repeatedly to
compute the remaining quotient bits. For unsigned single precision
divides, the DIVQ instruction is executed 16 times to produce 16 quotient
bits. For signed single precision divides, the DIVQ instruction is executed
15 times after the sign bit is computed by the DIVS operation. DIVQ
instruction shifts the AY0 register left by one bit so that the new quotient
bit can be moved into the LSB position. The status of the AQ bit generated
from the previous operation determines the ALU operation to calculate
the partial remainder. If AQ = 1, the ALU adds the divisor to the partial
remainder in AF. If AQ = 0, the ALU subtracts the divisor from the partial
remainder in AF. The ALU output R is offset loaded into AF just as with
the DIVS operation. The AQ bit is computed as the exclusive-OR of the
2 – 10
AX1
MUX
UPPER
DIVIDEND
MSB
DIVISOR
X
ALU
R = PASS Y
L
AY1 AF
S
B
16
MUX
MSB
Y
15 LSBs
15
LEFT SHIFT
AY0
LOWER
DIVIDEND
AQ