Short Read Cycle - Analog Devices adsp-2100 Manual

11 DMA Ports

11.3.4.3 Short Read Cycle

The host reads the contents of a ADSP-2181 internal memory location using
the IDMA short read cycle. The read cycle, shown in Figure 11.11, consists
of the following steps:
1. Host ensures that
2. Host asserts
contents of the location pointed to by the target IDMA address on the
IAD15-0 address/data bus.
3. ADSP-2181 deasserts
fetched.
4. Host detects the
DATA) from the IAD15-0 address/data bus, before the requested data
(READ DATA) is driven on the IAD address/data bus—not waiting for
the ADSP-2181 to assert the
deasserts
The host must do an initial "dummy" read, to make the ADSP-2181 put the
first data word (PREVIOUS DATA) on the IAD15-0 bus.
Note that IAL is low (inactive) and
read operation.
The IDMA Short Read and Long Read cycles provide different alternatives
for implementing your DMA transfers. Short reads are useful for hosts that
can handle the faster timing of these accesses, while long reads allow
slower hosts more time.
The IDMA short read cycle also serves as a single-location data buffer. If
you are using the ADSP-2181 in a multiprocessing environment, using this
buffer is one way to avoid tying up the IAD bus (waiting for
Warning: If an IDMA address latch cycle or a ADSP-2181 write to the
IDMA Control register occurs after a first Program Memory read cycle, the
IDMA port will lose the second half of the Program Memory word. The
ADSP-2181 treats the next host data on the IAD address/data bus as the
new contents of the IDMA Control Register.
11 – 20
IACK
line is low.
IRD IS
and (low), directing the ADSP-2181 to put the
IACK
line, indicating the requested data is being
IACK
line is now high and reads the data (PREVIOUS
IACK
IRD IS
and .
line. After reading the data, the host
IWR
is high (inactive) throughout the
IACK
signal).