Analog Devices adsp-2100 Manual page 296

The processor uses frame synchronization signals to tell the codec to send
and receive data. To transmit data to the codec, it sends a TFS0 pulse to
the FSR input of the codec and then outputs the eight bits on DT0 on the
next eight serial clock periods. The codec receives the data on its DR input.
Likewise, the processor initiates a data receive operation by sending an
RFS0 pulse to the codec's FSX input, which causes the codec to output
eight bits on its DX output on the next eight serial clock periods. The
processor receives the data on its DR0 input. The ADSP-21xx must be
programmed to use normal framing, 8-bit data words, and internal, active-
high frame sync generation.
The ADSP-21xx code shown in Listing 13.1 configures SPORT0 for
operation as required in this example:
• Internally generated serial clock
• 2.048 MHz serial clock frequency
• Both transmit and receive frame syncs required
• Use normal framing for both transmit and receive
• Internally generated transmit and receive frame syncs
• Both frame syncs active high
• Word length of eight bits
• µ-law companding
This code assumes the processor operating at 12.288 MHz. The code also
sets up the processor to request data from the codec at an 8 kHz rate (this
register is not initialized at reset and should always be written before the
SPORT is enabled if RFS is generated internally). The processor transmits
data as needed by the program it is executing.
AX0=0x6927;
DM(0x3FF6)=AX0;
AX0=2;
DM(0x3FF5)=AX0;
AX0=255;
DM(0x3FF4)=AX0;
AX0=0x1038;
DM(0x3FFF)=AX0;
Listing 13.1 Serial Port Initialization Example
Hardware Examples
{Int SCLK, RFS/TFS req, norm framing,}
{generate RFS, active HI, Mu-law, word length 8}
{value of SCLKDIV for 2.048 MHz}
{with a 12.888 MHz CLKOUT}
{RFSDIV=256, 256 SCLKs between}
{frame syncs, 8 kHz framing}
{enable SPORT0 only, leave defaults}
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