Analog Devices adsp-2100 Manual page 427

MULTIFUNCTION
15
ALU / MAC with DATA & PROGRAM MEMORY READ
Syntax:
<ALU> , AX0 = DM ( I0 , M0 ) , AY0
<MAC>
Description:
with a data memory read and a program memory read. The read
operations move the contents of the memory location to the destination
register. For this double data fetch, the destinations for data memory
reads are the X registers in the ALU and the MAC, and the destinations
for program memory reads are the Y registers. The addressing mode is
register indirect with post-modify. For linear (i.e. non-circular) indirect
addressing, the L register corresponding to the I register used must be
set to zero. The contents of the source are always right-justified in the
destination register after the read.
A multifunction instruction requires three items to be fetched from
memory: the instruction itself and two data words. No extra cycle is
needed to execute the instruction as long as only one of the fetches is from
external memory.
If two off-chip accesses are required, however—the instruction fetch and
one data fetch, for example, or data fetches from both program and data
memory—then one overhead cycle occurs. In this case the program
memory access occurs first, then the data memory access. If three off-chip
accesses are required—the instruction fetch as well as data fetches from
both program and data memory—then two overhead cycles occur.
The computation must be unconditional. All ALU and MAC operations
are permitted except the DIVS and DIVQ instructions. The results of the
computation must be written into the R register of the computational unit;
ALU results to AR, MAC results to MR.
The fundamental principle governing multifunction instructions is that
registers (and memory) are read at the beginning of the processor cycle
and written at the end of the cycle. The normal left-to-right order of
clauses (computation first, memory reads second) is intended to imply
this. In fact, you may code this instruction with the order of clauses
altered. The assembler produces a warning, but the results are identical at
the opcode level. If you turn off semantics checking in the assembler (–s
switch) the warning is not issued.
15 – 104
AX1 I1
MX0 I2
MX1 I3
This instruction combines an ALU or a MAC operation
= PM ( I4 , M4 ) ;
M1 AY1
M2 MY0
M3 MY1
I5 M5
I6 M6
I7 M7