Figure 2.1.1B Sample Linear Addressing - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

Address generation types
2
The F MC-16LX CPU has two address generation methods. One is the linear method in which an entire
24-bit address is specified by an instruction. The other method is the bank method in which the high-order
eight bits of an address is specified by an appropriate bank register while the low-order 16 bits of the same
address is specified by an instruction.
There are two types of linear method. One specifies a 24-bit address directly by using operands. The other
method cites the low-order 24 bits of a 32-bit general-purpose register value as an address. (See Figure
2.1.1b.)
Example 1 Linear method (24-bit operand specification)
JMPP 123456H
Old program counter
+ program bank
New program counter
+ program bank
Example 2 Linear method (32-bit register indirect specification)
MOV A, @RL1+7
Bank addressing types
In the bank method, the 16-Mbyte space is divided into 256 64-Kbyte banks. The following five bank
registers are used to specify the banks corresponding to each space:
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
MB90580 Series
17 452D
12
3456
XXXX
Old AL
(The high-order eight bits are ignored.)
003A
New AL

Figure 2.1.1b Sample linear addressing

17452D
H
123456
H
090700
H
+7
RL1
2.1 CPU
JMPP 123456
H
Next instruction
3A
240906F9
Chapter 2: CPU 17