Uart Block Diagram - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 21 UART
21.2

UART Block Diagram

UART is composed of the following block.
UART Block Diagram
Dedicated baud
rater generator
UART prescalor
control register
(UTCR0 to UTCR3)
UART prescalor
reload register
(UTRLR0 to UTRLR3)
Pin
SCK0 to SCK3
External clock
Pin
SIN0 to SIN3
Receive state
478
Figure 21.2-1 UART Block Diagram
Receive clock
Start bit
detection circuit
Receive bit
counter
Receive parity
counter
Receiving
shift register
SIDR0 to SIDR3
judge circuit
MD1
MD0
SCKL
SMR0 to
M2L2
SMR3
M2L1
register
M2L0
SCKE
SOE
Control bus
Transfer clock
Receive
control
circuit
Transmit start
circuit
Transmit bit
counter
Transmit parity
counter
Transmit
shift register
Receiving
end
SODR0 to SODR3
2
F MC - 16LX Bus
PEN
P
SBL
SCR0 to
CL
SCR3
A/D
register
REC
RXE
TXE
Receive
interrupt signal
Transmit
interrupt signal
Transmit
control
circuit
Pin
SOT0 to SOT3
Transmission
end
Receive error
generation signal
2 OS · µDMAC
for EI
(to CPU)
PE
ORE
FRE
SSR0 to
RDRF
SSR3
TDRE
register
BDS
RIE
TIE