Fig. 1.2 Block Diagram - Fujitsu MB89140 Series Hardware Manual

1.3 BLOCK DIAGRAM
X0
X1
P70, P71
X0A
Port
X1A
7
CMOS input port
P23/WDG
CMOS output port
P22
Port
P21/PWO0
2
P20
MODA
AV
CC
AV
SS
P17/ADST
4
P14 to P16
Port
4
0/1
P13/ANB to
P10/AN8
8
P07/AN7 to
CMOS output port
P00/AN0
(Max. 512
2
F
CPU
(Max. 16 K
GENERAL
Internal bus
Main clock oscillator
(Max. 8 MHz)
Clock control
Sub clock oscillator
(32.768 kHz)
8-bit PWM timer
Mode control
10-bit A/D converter
RAM
8 bit )
MC-8L
ROM
8 bit)

Fig. 1.2 Block Diagram

Time-base timer
High-withstand-voltage
High-withstand-voltage
High-withstand-voltage
8-bit serial
12-bit MPG
8/16-bit timer/counter
External interrupt
input
CMOS I/O port
Other pins
V , V
CC SS
1-7
Buzzer
BZ
P60 to P67
port 6
P50 to P57
port 5
P40 to P47
port 4
VFD
P32/SCK
P33/SO
P34/SI
P30/TRG/INT0
P37/DTTI
P3/PWO1
Port
3
P35/EC
P31/INT1