Table of Contents
Advertisement
Debug support (DBG)
38.14
CPU2 breakpoint unit (BPU)
The BPU allows hardware breakpoints to be set. It contains eight comparators which
monitor the instruction fetch address and return a breakpoint instruction when a match is
detected.The CPU2 PBU does not support flash memory patch functionality.
38.14.1
BPU control register (BPU_CTRLR)
Address offset: 0x000
Reset value: 0x0000 0080
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
r
r
r
Bits 31:15 Reserved, must be kept at reset value.
Bits 11:8 NUM_LIT[3:0]: number of literal address comparators supported (read only)
0x0: No literal comparators supported.
Bit 14,13,12,7,6,5,4 NUM_CODE[6:0]: number of instruction address comparators supported - least significant bits
(read only)
0x8: 8 instruction comparators supported
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 KEY: write protect key
A write to BPU_CTRLR register is ignored if this bit is not set to 1.
Bit 0 ENABLE: BPU enable
0: Disabled
1: Enabled
38.14.2
BPU remap register (BPU_REMAPR)
Address offset: 0x004
Reset value: 0x0000 0000
31
30
29
Res.
Res.
RMPSPT
r
15
14
13
Res.
Res.
Res.
1428/1450
27
26
25
Res.
Res.
Res.
11
10
9
NUM_LIT[3:0]
r
r
r
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
NUM_CODE[3:0]
r
r
r
r
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0453 Rev 5
20
19
18
Res.
Res.
Res.
4
3
2
Res.
Res.
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0453
17
16
Res.
Res.
1
0
KEY
ENABLE
rw
rw
17
16
Res.
Res.
1
0
Res.
Res.
Advertisement
Chapters
Table of Contents
Need help?
Do you have a question about the STM32WL5 Series and is the answer not in the manual?