Table of Contents
Advertisement
RM0453
38.13.18 CPU2 ROM2 CoreSight component identity register 0
(C2ROM2_CIDR0)
Address offset: 0xFF0
Reset value: 0x0000 000D
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[7:0]: component ID bits [7:0]
0x0D: Common ID value
38.13.19 CPU2 ROM2 CoreSight peripheral identity register 1
(C2ROM2_CIDR1)
Address offset: 0xFF4
Reset value: 0x0000 0010
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 CLASS[3:0]: Component ID bits [15:12] - component class
0x1: ROM table component
Bits 3:0 PREAMBLE[11:8]: Component ID bits [11:8]
0x0: Common ID value
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0453 Rev 5
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
PREAMBLE[7:0]
r
r
r
r
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
CLASS[3:0]
r
r
r
r
Debug support (DBG)
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
r
r
r
r
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
PREAMBLE[11:8]
r
r
r
r
1425/1450
1435
Advertisement
Chapters
Table of Contents
Need help?
Do you have a question about the STM32WL5 Series and is the answer not in the manual?