STMicroelectronics STM32WL5 Series Reference Manual page 1427

RM0453
Table 286. CPU2 ROM table register map and reset values (continued)
Offset Register name
C2ROM2_PIDR0
0xFE0
Reset value
C2ROM2_PIDR1
0xFE4
Reset value
C2ROM2_PIDR2
0xFE8
Reset value
C2ROM2_PIDR3
0xFEC
Reset value
C2ROM2_CIDR0
0xFF0
Reset value
C2ROM2_CIDR1
0xFF4
Reset value
C2ROM2_CIDR2
0xFF8
Reset value
C2ROM2_CIDR3
0xFFC
Reset value
Refer to Section 38.13: CPU2 ROM tables for the register boundary addresses.
RM0453 Rev 5
Debug support (DBG)
PARTNUM[7:0]
1 1 0 0 0 0 0
JEP106ID PARTNUM
[3:0] [11:8]
1 0 1 1 0 1 0
0 0 0 0 1 0 1
REVAND[3:0] CMOD[3:0]
0 0 0 0 0 0 0
PREAMBLE[7:0]
0 0 0 0 1 1 0
PREAMBLE
CLASS[3:0]
[11:8]
0 0 0 1 0 0 0
PREAMBLE[19:12]
0 0 0 0 0 1 0
PREAMBLE[27:20]
1 0 1 1 0 0 0
1427/1450
0
0
1
0
1
0
1
1
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