Table of Contents
Advertisement
RM0453
Bit 0 DBG_TIM2_STOP: TIM2 stop in CPU2 debug
0: Normal operation. TIM2 continues to operate while CPU2 is in debug mode.
1: Stop in debug. TIM2 is frozen while CPU2 is in debug mode.
38.12.5
DBGMCU CPU1 APB1 peripheral freeze register 2
(DBGMCU_APB1FZR2)
Address offset: 0x044
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 DBG_LPTIM3_STOP: LPTIM3 stop in CPU1 debug
0: Normal operation. LPTIM3 continues to operate while CPU1 is in debug mode.
1: Stop in debug. LPTIM3 is frozen while CPU1 is in debug mode.
Bit 5 DBG_LPTIM2_STOP: LPTIM2 stop in CPU1 debug
0: Normal operation. LPTIM2 continues to operate while CPU1 is in debug mode.
1: Stop in debug. LPTIM2 is frozen while CPU1 is in debug mode.
Bits 4:0 Reserved, must be kept at reset value.
38.12.6
DBGMCU CPU2 APB1 peripheral freeze register 2
(DBGMCU_C2APB1FZR2)
Address offset: 0x048
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 DBG_LPTIM3_STOP: LPTIM3 stop in CPU2 debug
0: Normal operation. LPTIM3 continues to operate while CPU2 is in debug mode.
1: Stop in debug. LPTIM3 is frozen while CPU2 is in debug mode.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
DBG_
DBG_
Res.
Res.
LPTIM3
LPTIM2
_STOP
_STOP
rw
24
23
22
Res.
Res.
Res.
8
7
6
DBG_
DBG_
Res.
Res.
LPTIM3
LPTIM2
_STOP
_STOP
rw
RM0453 Rev 5
Debug support (DBG)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
rw
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
rw
17
16
Res.
Res.
1
0
Res.
Res.
17
16
Res.
Res.
1
0
Res.
Res.
1411/1450
1435
Advertisement
Chapters
Table of Contents
Need help?
Do you have a question about the STM32WL5 Series and is the answer not in the manual?