Texas Instruments AM335 Series Manuals

Manuals and User Guides for Texas Instruments AM335 Series. We have 5 Texas Instruments AM335 Series manuals available for free PDF download: Technical Reference Manual, Design Manual, Quick Start Manual

Texas Instruments AM335 Series Quick Start Manual

Texas Instruments AM335x - Evaluation Module Quick Start Guide

Brand: Texas Instruments | Category: Motherboard | Size: 13 MB

Texas Instruments AM335 Series Technical Reference Manual (4161 pages)

ARM Cortex-A8

Brand: Texas Instruments | Category: Computer Hardware | Size: 18 MB

List of Figures

16
- Table of Contents
  16
Table of Contents

122
Table of Contents

136
- Device Features
  150
- Device_Id (Address 0X44E10600) Bit Field Descriptions
  151
- DEV_FEATURE (Address 0X44E10604) Register Values
  152
- L3 Memory Map
  155
- L4_WKUP Peripheral Memory Map
  157
- L4_PER Peripheral Memory Map
  158
- L4 Fast Peripheral Memory Map
  162
- Microprocessor Unit (MPU) Subsystem
  165
- Microprocessor Unit (MPU) Subsystem Signal Interface
  167
- MPU Subsystem Clock Frequencies
  168
- MPU Subsystem Clocking Scheme
  168
- Reset Scheme of the MPU Subsystem
  169
- ARM Core Supported Features
  171
- MPU Subsystem Power Domain Overview
  172
- Overview of the MPU Subsystem Power Domain
  172
- MPU Power States
  173
- MPU Subsystem Operation Power Modes
  174
- 5.2.1 SGX530 Connectivity Attributes
  182
- SGX530 Clock Signals
  182
- SGX530 Integration
  182
- SGX Block Diagram
  184
- Interrupt Controller Block Diagram
  187
- IRQ/FIQ Processing Sequence
  193
- Nested IRQ/FIQ Processing Sequence
  197
- ARM Cortex-A8 Interrupts
  199
- Timer and Ecap Event Capture
  203
- Intc Registers
  204
- INTC_REVISION Register
  206
- INTC_REVISION Register Field Descriptions
  206
- INTC_SYSCONFIG Register
  207
- INTC_SYSCONFIG Register Field Descriptions
  207
- INTC_SYSSTATUS Register
  208
- INTC_SYSSTATUS Register Field Descriptions
  208
- INTC_SIR_IRQ Register
  209
- INTC_SIR_IRQ Register Field Descriptions
  209
- INTC_SIR_FIQ Register
  210
- INTC_SIR_FIQ Register Field Descriptions
  210
- INTC_CONTROL Register
  211
- INTC_CONTROL Register Field Descriptions
  211
- INTC_PROTECTION Register
  212
- INTC_PROTECTION Register Field Descriptions
  212
- INTC_IDLE Register
  213
- INTC_IDLE Register Field Descriptions
  213
- INTC_IRQ_PRIORITY Register
  214
- INTC_IRQ_PRIORITY Register Field Descriptions
  214
- INTC_FIQ_PRIORITY Register
  215
- INTC_FIQ_PRIORITY Register Field Descriptions
  215
- INTC_THRESHOLD Register
  216
- INTC_THRESHOLD Register Field Descriptions
  216
- INTC_ITR0 Register
  217
- INTC_ITR0 Register Field Descriptions
  217
- INTC_MIR0 Register
  218
- INTC_MIR0 Register Field Descriptions
  218
- INTC_MIR_CLEAR0 Register
  219
- INTC_MIR_CLEAR0 Register Field Descriptions
  219
- INTC_MIR_SET0 Register
  220
- INTC_MIR_SET0 Register Field Descriptions
  220
- INTC_ISR_SET0 Register
  221
- INTC_ISR_SET0 Register Field Descriptions
  221
- INTC_ISR_CLEAR0 Register
  222
- INTC_ISR_CLEAR0 Register Field Descriptions
  222
- INTC_PENDING_IRQ0 Register
  223
- INTC_PENDING_IRQ0 Register Field Descriptions
  223
- INTC_PENDING_FIQ0 Register
  224
- INTC_PENDING_FIQ0 Register Field Descriptions
  224
- INTC_ITR1 Register
  225
- INTC_ITR1 Register Field Descriptions
  225
- INTC_MIR1 Register
  226
- INTC_MIR1 Register Field Descriptions
  226
- INTC_MIR_CLEAR1 Register
  227
- INTC_MIR_CLEAR1 Register Field Descriptions
  227
- INTC_MIR_SET1 Register
  228
- INTC_MIR_SET1 Register Field Descriptions
  228
- INTC_ISR_SET1 Register
  229
- INTC_ISR_SET1 Register Field Descriptions
  229
- INTC_ISR_CLEAR1 Register
  230
- INTC_ISR_CLEAR1 Register Field Descriptions
  230
- INTC_PENDING_IRQ1 Register
  231
- INTC_PENDING_IRQ1 Register Field Descriptions
  231
- INTC_PENDING_FIQ1 Register
  232
- INTC_PENDING_FIQ1 Register Field Descriptions
  232
- INTC_ITR2 Register
  233
- INTC_ITR2 Register Field Descriptions
  233
- INTC_MIR2 Register
  234
- INTC_MIR2 Register Field Descriptions
  234
- INTC_MIR_CLEAR2 Register
  235
- INTC_MIR_CLEAR2 Register Field Descriptions
  235
- INTC_MIR_SET2 Register
  236
- INTC_MIR_SET2 Register Field Descriptions
  236
- INTC_ISR_SET2 Register
  237
- INTC_ISR_SET2 Register Field Descriptions
  237
- INTC_ISR_CLEAR2 Register
  238
- INTC_ISR_CLEAR2 Register Field Descriptions
  238
- INTC_PENDING_IRQ2 Register
  239
- INTC_PENDING_IRQ2 Register Field Descriptions
  239
- INTC_PENDING_FIQ2 Register
  240
- INTC_PENDING_FIQ2 Register Field Descriptions
  240
- INTC_ITR3 Register
  241
- INTC_ITR3 Register Field Descriptions
  241
- INTC_MIR3 Register
  242
- INTC_MIR3 Register Field Descriptions
  242
- INTC_MIR_CLEAR3 Register
  243
- INTC_MIR_CLEAR3 Register Field Descriptions
  243
- INTC_MIR_SET3 Register
  244
- INTC_MIR_SET3 Register Field Descriptions
  244
- INTC_ISR_SET3 Register
  245
- INTC_ISR_SET3 Register Field Descriptions
  245
- INTC_ISR_CLEAR3 Register
  246
- INTC_ISR_CLEAR3 Register Field Descriptions
  246
- INTC_PENDING_IRQ3 Register
  247
- INTC_PENDING_IRQ3 Register Field Descriptions
  247
- INTC_PENDING_FIQ3 Register
  248
- INTC_PENDING_FIQ3 Register Field Descriptions
  248
- INTC_ILR0 to INTC_ILR127 Register
  249
- INTC_ILR0 to INTC_ILR127 Register Field Descriptions
  249
- GPMC Block Diagram
  253
- Unsupported GPMC Features
  253
- GPMC Clock Signals
  254
- GPMC Connectivity Attributes
  254
- GPMC Integration
  254
- GPMC Signal List
  255
- GPMC Pin Multiplexing Options
  256
- GPMC Signals
  256
- GPMC to 16-Bit Address/Data-Multiplexed Memory
  258
- GPMC to 16-Bit Non-Multiplexed Memory
  259
- GPMC to 8-Bit NAND Device
  259
- GPMC Clocks
  261
- GPMC Local Power Management Features
  261
- Gpmc_Config1_I
  261
- GPMC Interrupt Events
  262
- Chip-Select Address Mapping and Decoding Mask
  264
- Wait Behavior During an Asynchronous Single Read Access (Gpmcfclkdivider = 1)
  267
- Wait Behavior During a Synchronous Read Burst Access
  269
- Read to Read / Write for an Address-Data Multiplexed Device, on Different CS, with Bus Turnaround
  271
- Read to Read for an Address-Data Multiplexed Device, on Different CS, Without Bus Turnaround (Cs0N Attached to Fast Device)
  271
- Read to Read / Write for a Address-Data or AAD-Multiplexed Device, on same CS, with Bus Turnaround
  272
- Idle Cycle Insertion Configuration
  273
- Gpmc_Timeout_Control
  275
- Asynchronous Single Read Operation on an Address/Data Multiplexed Device
  281
- Two Asynchronous Single Read Accesses on an Address/Data Multiplexed Device (32-Bit Read Split into 2 × 16-Bit Read)
  282
- Asynchronous Single Write on an Address/Data-Multiplexed Device
  283
- Asynchronous Single-Read on an AAD-Multiplexed Device
  284
- Asynchronous Single Write on an AAD-Multiplexed Device
  286
- Synchronous Single Read (GPMCFCLKDIVIDER = 0)
  288
- Synchronous Single Read (GPMCFCLKDIVIDER = 1)
  289
- Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 0)
  291
- Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 1)
  292
- Synchronous Single Write on an Address/Data-Multiplexed Device
  293
- Synchronous Multiple Write (Burst Write) in Address/Data-Multiplexed Mode
  294
- Synchronous Multiple Write (Burst Write) in Address/Address/Data-Multiplexed Mode
  295
- Asynchronous Single Read on an Address/Data-Nonmultiplexed Device
  297
- Asynchronous Single Write on an Address/Data-Nonmultiplexed Device
  298
- Asynchronous Multiple (Page Mode) Read
  299
- Chip-Select Configuration for NAND Interfacing
  302
- NAND Command Latch Cycle
  304
- NAND Address Latch Cycle
  305
- NAND Data Read Cycle
  306
- NAND Data Write Cycle
  307
- Gpmc_Ecc_Config
  310
- Gpmc_Ecc_Control
  310
- ECC Enable Settings
  311
- Hamming Code Accumulation Algorithm (1 of 2)
  311
- ECC Computation for a 256-Byte Data Stream (Read or Write)
  312
- Hamming Code Accumulation Algorithm (2 of 2)
  312
- ECC Computation for a 512-Byte Data Stream (Read or Write)
  313
- Word16 ECC Computation
  314
- Aligned Message Byte Mapping in 8-Bit NAND
  316
- Flattened BCH Codeword Mapping (512 Bytes + 104 Bits)
  316
- Aligned Message Byte Mapping in 16-Bit NAND
  317
- Aligned Nibble Mapping of Message in 16-Bit NAND
  317
- Aligned Nibble Mapping of Message in 8-Bit NAND
  317
- Misaligned Nibble Mapping of Message in 8-Bit NAND
  317
- Misaligned Nibble Mapping of Message in 16-Bit NAND (1 Unused Nibble)
  318
- Misaligned Nibble Mapping of Message in 16-Bit NAND (2 Unused Nibble)
  318
- Misaligned Nibble Mapping of Message in 16-Bit NAND (3 Unused Nibble)
  318
- Manual Mode Sequence and Mapping
  319
- NAND Page Mapping and ECC: Per-Sector Schemes
  324
- NAND Page Mapping and ECC: Pooled Spare Schemes
  325
- NAND Page Mapping and ECC: Per-Sector Schemes, with Separate ECC
  326
- Gpmc_Prefetch_Config1
  329
- Prefetch Mode Configuration
  329
- Write-Posting Mode Configuration
  331
- Gpmc_Prefetch_Status
  332
- NAND Read Cycle Optimization Timing Description
  333
- Programming Model Top-Level Diagram
  336
- GPMC Configuration in NAND Mode
  337
- GPMC Configuration in nor Mode
  337
- NOR Chip-Select Configuration
  337
- NOR Memory Type
  337
- NOR Timings Configuration
  337
- Prefetch and Write-Posting Engine
  337
- Reset GPMC
  337
- WAIT Pin Configuration
  338
- Asynchronous Read and Write Operations
  339
- ECC Engine
  339
- Enable Chip-Select
  339
- NAND Chip-Select Configuration
  339
- NAND Memory Type
  339
- Enable Chip-Select
  341
- WAIT Pin Configuration
  341
- Access Type Parameters Check List Table
  342
- Mode Parameters Check List Table
  342
- NOR Interfacing Timing Parameters Diagram
  343
- Gpmc_Config3_I
  344
- Gpmc_Config4_I
  344
- NAND Formulas Description Table
  346
- NAND Command Latch Cycle Timing Simplified Example
  347
- Synchronous nor Formulas Description Table
  347
- Synchronous nor Single Read Simplified Example
  352
- Asynchronous nor Formulas Description Table
  353
- Asynchronous nor Single Write Simplified Example
  354
- Use Case
  355
- GPMC Connection to an External nor Flash Memory
  356
- Useful Timing Parameters on the Memory Side
  357
- Calculating GPMC Timing Parameters
  358
- Synchronous Burst Read Access (Timing Parameters in Clock Cycles)
  358
- AC Characteristics for Asynchronous Read Access
  359
- Asynchronous Single Read Access (Timing Parameters in Clock Cycles)
  360
- GPMC Timing Parameters for Asynchronous Read Access
  360
- AC Characteristics for Asynchronous Single Write (Memory Side)
  361
- Asynchronous Single Write Access (Timing Parameters in Clock Cycles)
  362
- GPMC Timing Parameters for Asynchronous Single Write
  362
- NAND Interface Bus Operations Summary
  363
- NOR Interface Bus Operations Summary
  363
- GPMC Registers
  366
- Gpmc_Revision
  367
- Gpmc_Sysconfig
  367
- Gpmc_Sysstatus
  368
- GPMC_IRQSTATUS Field Descriptions
  369
- Gpmc_Irqenable
  370
- GPMC_ERR_ADDRESS Field Descriptions
  371
- GPMC_TIMEOUT_CONTROL Field Descriptions
  371
- Gpmc_Err_Type
  372
- GPMC_CONFIG Field Descriptions
  373
- Gpmc_Status
  374
- Gpmc_Config
  375
- Gpmc_Config1_I Field Descriptions
  375
- Gpmc_Config2_I
  377
- Gpmc_Config2_I Field Descriptions
  377
- Gpmc_Config3_I Field Descriptions
  378
- Gpmc_Config4_I Field Descriptions
  380
- Gpmc_Config5_I
  382
- Gpmc_Config5_I Field Descriptions
  382
- Gpmc_Config6_I
  383
- Gpmc_Config6_I Field Descriptions
  383
- Gpmc_Config7_I
  384
- Gpmc_Config7_I Field Descriptions
  384
- Gpmc_Nand_Address_I
  385
- Gpmc_Nand_Address_I Field Descriptions
  385
- Gpmc_Nand_Command_I
  385
- Gpmc_Nand_Command_I Field Descriptions
  385
- Gpmc_Nand_Data_I
  385
- Gpmc_Nand_Data_I Field Descriptions
  385
- GPMC_PREFETCH_CONFIG1 Field Descriptions
  386
- Gpmc_Prefetch_Config2
  388
- Gpmc_Prefetch_Control
  388
- GPMC_PREFETCH_STATUS Field Descriptions
  389
- GPMC_ECC_CONFIG Field Descriptions
  390
- GPMC_ECC_CONTROL Field Descriptions
  391
- GPMC_ECC_SIZE_CONFIG Field Descriptions
  392
- Gpmc_Ecc_Size_Config
  393
- Gpmc_Eccj_Result Field Descriptions
  394
- Gpmc_Bch_Result0_I
  395
- Gpmc_Bch_Result0_I Field Descriptions
  395
- Gpmc_Bch_Result1_I
  395
- Gpmc_Bch_Result1_I Field Descriptions
  395
- Gpmc_Bch_Result2_I
  395
- Gpmc_Bch_Result2_I Field Descriptions
  395
- Gpmc_Bch_Result3_I
  396
- Gpmc_Bch_Result3_I Field Descriptions
  396
- Gpmc_Bch_Result4_I
  396
- Gpmc_Bch_Result4_I Field Descriptions
  396
- Gpmc_Bch_Swdata
  396
- Gpmc_Bch_Result5_I
  397
- Gpmc_Bch_Result5_I Field Descriptions
  397
- Gpmc_Bch_Result6_I
  397
- Gpmc_Bch_Result6_I Field Descriptions
  397
- OCMC RAM Clock Signals
  399
- OCMC RAM Connectivity Attributes
  399
- OCMC RAM Integration
  399
- Unsupported EMIF Features
  401
- EMIF Clock Signals
  402
- EMIF Connectivity Attributes
  402
- EMIF Pin List
  402
- Ddr2/3/Mddr Memory Controller Signal Descriptions
  404
- Ddr2/3/Mddr Memory Controller Signals
  404
- Timing Parameters
  405
- Ddr2/3/Mddr Subsystem Block Diagram
  406
- Ddr2/3/Mddr Memory Controller FIFO Block Diagram
  407
- Digital Filter Configuration
  408
- IBANK, RSIZE and PAGESIZE Fields Information
  409
- OCP Address to Ddr2/3/Mddr Address Mapping for REG_IBANK_POS=0 and REG_EBANK_POS=0
  410
- OCP Address to Ddr2/3/Mddr Address Mapping for REG_IBANK_POS=1 and REG_EBANK_POS=0
  411
- OCP Address to Ddr2/3/Mddr Address Mapping for REG_IBANK_POS=2 and REG_EBANK_POS=0
  411
- OCP Address to Ddr2/3/Mddr Address Mapping for REG_IBANK_POS=0 and REG_EBANK_POS=1
  412
- OCP Address to Ddr2/3/Mddr Address Mapping for REG_IBANK_POS=3 and REG_EBANK_POS=0
  412
- OCP Address to Ddr2/3/Mddr Address Mapping for REG_IBANK_POS=3 and REG_EBANK_POS=1
  413
- Refresh Modes
  416
- Filter Configurations for Performance Counters
  417
- 7.3.5 EMIF4D Registers
  422
- EMIF_MOD_ID_REV Register
  424
- EMIF_MOD_ID_REV Register Field Descriptions
  424
- STATUS Register
  425
- STATUS Register Field Descriptions
  425
- SDRAM_CONFIG Register
  426
- SDRAM_CONFIG Register Field Descriptions
  426
- SDRAM_CONFIG_2 Register
  428
- SDRAM_REF_CTRL Register
  429
- SDRAM_REF_CTRL Register Field Descriptions
  429
- SDRAM_REF_CTRL_SHDW Register
  430
- SDRAM_REF_CTRL_SHDW Register Field Descriptions
  430
- SDRAM_TIM_1 Register
  431
- SDRAM_TIM_1_SHDW Register
  432
- SDRAM_TIM_1_SHDW Register Field Descriptions
  432
- SDRAM_TIM_2 Register
  433
- SDRAM_TIM_2_SHDW Register
  434
- SDRAM_TIM_2_SHDW Register Field Descriptions
  434
- SDRAM_TIM_3 Register
  435
- SDRAM_TIM_3_SHDW Register
  436
- SDRAM_TIM_3_SHDW Register Field Descriptions
  436
- PWR_MGMT_CTRL Register
  437
- PWR_MGMT_CTRL Register Field Descriptions
  437
- PWR_MGMT_CTRL_SHDW Register
  439
- PWR_MGMT_CTRL_SHDW Register Field Descriptions
  439
- Interface Configuration Register
  440
- Interface Configuration Register Field Descriptions
  440
- Interface Configuration Value 1 Register
  441
- Interface Configuration Value 1 Register Field Descriptions
  441
- Interface Configuration Value 2 Register
  442
- Interface Configuration Value 2 Register Field Descriptions
  442
- PERF_CNT_1 Register
  443
- PERF_CNT_2 Register
  444
- PERF_CNT_CFG Register
  445
- PERF_CNT_SEL Register
  446
- PERF_CNT_TIM Register
  447
- READ_IDLE_CTRL Register
  448
- READ_IDLE_CTRL Register Field Descriptions
  448
- READ_IDLE_CTRL_SHDW Register
  449
- READ_IDLE_CTRL_SHDW Register Field Descriptions
  449
- IRQSTATUS_RAW_SYS Register
  450
- IRQSTATUS_SYS Register
  451
- IRQENABLE_SET_SYS Register
  452
- IRQENABLE_CLR_SYS Register
  453
- ZQ_CONFIG Register
  454
- ZQ_CONFIG Register Field Descriptions
  454
- Read-Write Leveling Ramp Window Register
  455
- Read-Write Leveling Ramp Window Register Field Descriptions
  455
- Read-Write Leveling Ramp Control Register
  456
- Read-Write Leveling Ramp Control Register Field Descriptions
  456
- Read-Write Leveling Control Register
  457
- Read-Write Leveling Control Register Field Descriptions
  457
- DDR_PHY_CTRL_1 Register
  458
- DDR_PHY_CTRL_1 Register Field Descriptions
  459
- DDR_PHY_CTRL_1_SHDW Register
  460
- DDR_PHY_CTRL_1_SHDW Register Field Descriptions
  460
- Priority to Class of Service Mapping Register
  462
- Priority to Class of Service Mapping Register Field Descriptions
  462
- Connection ID to Class of Service 1 Mapping Register
  463
- Connection ID to Class of Service 1 Mapping Register Field Descriptions
  463
- Connection ID to Class of Service 2 Mapping Register
  464
- Connection ID to Class of Service 2 Mapping Register Field Descriptions
  464
- Read Write Execution Threshold Register
  466
- Read Write Execution Threshold Register Field Descriptions
  466
- Memory-Mapped Registers for Ddr2/3/Mddr PHY
  467
- CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0) Field Descriptions
  469
- DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register
  469
- DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register( CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0)
  469
- DDR PHY Command 0/1/2 Address/Command Slave Ratio Register
  469
- DDR PHY Command 0/1/2 Address/Command Slave Ratio Register (CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0) Field Descriptions
  469
- CMD0/1/2_REG_PHY_INVERT_CLKOUT_0) Field Descriptions
  470
- DDR PHY Command 0/1/2 Invert Clockout Selection Register
  470
- DDR PHY Command 0/1/2 Invert Clockout Selection Register( CMD0/1/2_REG_PHY_INVERT_CLKOUT_0)
  470
- DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register
  470
- DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register (DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0) Field Descriptions
  470
- DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) Field Descriptions
  471
- DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register
  471
- DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register( DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0) Field Descriptions
  471
- DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register
  471
- DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register ( DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0)
  471
- DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
  472
- DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register (DATA0_REG_PHY_GATELVL_INIT_RATIO_0) Field Descriptions
  472
- DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
  472
- (DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) Field Descriptions
  473
- DDR PHY Data Macro 0/1 DQS Gate Slave Ratio Register
  473
- DDR PHY Data Macro 0/1 DQS Gate Slave Ratio Register(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0)
  473
- DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register
  473
- DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register (DATA0/1_REG_PHY_GATELVL_INIT_MODE_0) Field Descriptions
  473
- DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
  474
- DDR PHY Data Macro 0/1 Write Data Slave Ratio Register (DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0) Field Descriptions
  474
- DDR PHY Data Macro 0/1 Delay Selection Register (DATA0/1_REG_PHY_USE_RANK0_DELAYS)
  475
- ELM Clock Signals
  477
- ELM Connectivity Attributes
  477
- ELM Integration
  477
- Local Power Management Features
  478
- Elm_Location_Status_I Value Decoding Table
  480
- ELM Processing Completion for Continuous Mode
  481
- ELM Processing Initialization
  481
- ELM Processing Completion for
  482
- Use Case: Continuous Mode
  482
- 7.4.5 ELM Registers
  487
- ELM Revision Register (ELM_REVISION)
  488
- ELM System Configuration Register (ELM_SYSCONFIG)
  488
- ELM System Status Register (ELM_SYSSTATUS)
  489
- ELM Interrupt Status Register (ELM_IRQSTATUS)
  490
- ELM Interrupt Status Register (ELM_IRQSTATUS) Field Descriptions
  491
- ELM Interrupt Enable Register (ELM_IRQENABLE)
  492
- ELM Location Configuration Register (ELM_LOCATION_CONFIG)
  493
- ELM Page Definition Register (ELM_PAGE_CTRL)
  494
- Elm_Syndrome_Fragment_0_I Register
  495
- Elm_Syndrome_Fragment_1_I Register
  495
- Elm_Syndrome_Fragment_2_I Register
  495
- Elm_Syndrome_Fragment_3_I Register
  496
- Elm_Syndrome_Fragment_4_I Register
  496
- Elm_Syndrome_Fragment_5_I Register
  496
- Elm_Location_Status_I Register
  497
- Elm_Syndrome_Fragment_6_I Register
  497
- ELM_ERROR_LOCATION_0-15_I Registers
  498
- ELM_ERROR_LOCATION_0-15_I Registers Field Descriptions
  498
- Functional and Interface Clocks
  500
- Master Module Standby-Mode Settings
  501
- Master Module Standby Status
  502
- Module Idle Mode Settings
  502
- Idle States for a Slave Module
  503
- Slave Module Mode Settings in PRCM
  503
- Module Clock Enabling Condition
  504
- Clock Domain Functional Clock States
  505
- Clock Domain State Transitions
  505
- Generic Clock Domain
  505
- Clock Domain States
  506
- Clock Transition Mode Settings
  506
- Generic Power Domain Architecture
  507
- States of a Logic Area in a Power Domain
  507
- States of a Memory Area in a Power Domain
  507
- Power Domain Control and Status Registers
  508
- Typical Power Modes
  509
- High Level System View for RTC-Only Mode
  512
- USB Wakeup Use Cases Supported in System Sleep States
  513
- System Level View of Power Management of Cortex A8 MPU and Cortex M3
  515
- IPC Mechanism
  516
- Output Clocks before Lock and During Relock Modes
  521
- Output Clocks in Locked Condition
  521
- Basic Structure of the ADPLLLJ
  522
- Output Clocks before Lock and During Relock Modes
  523
- Output Clocks in Locked Condition
  523
- Core PLL
  525
- Core PLL Typical Frequencies (Mhz)
  526
- PLL and Clock Frequences
  526
- Bus Interface Clocks
  527
- Per PLL Typical Frequencies (Mhz)
  528
- Peripheral PLL Structure
  528
- MPU Subsystem PLL Structure
  530
- Display PLL Structure
  531
- DDR PLL Structure
  532
- CLKOUT Signals
  533
- Watchdog Timer Clock Selection
  533
- Timer Clock Selection
  534
- RTC, VTP, and Debounce Clock Selection
  535
- Reset Sources
  536
- External System Reset
  538
- Warm Reset Sequence (External Warm Reset Source)
  539
- Warm Reset Sequence (Internal Warm Reset Source)
  540
- Core Logic Voltage and Power Domains
  545
- Power Domain of Various Modules
  545
- Power Domain State Table
  545
- Cm_Per Registers
  548
- CM_PER_L4LS_CLKSTCTRL Register
  550
- CM_PER_L4LS_CLKSTCTRL Register Field Descriptions
  550
- CM_PER_L3S_CLKSTCTRL Register
  552
- CM_PER_L3S_CLKSTCTRL Register Field Descriptions
  552
- CM_PER_L4FW_CLKSTCTRL Register
  553
- CM_PER_L4FW_CLKSTCTRL Register Field Descriptions
  553
- CM_PER_L3_CLKSTCTRL Register
  554
- CM_PER_L3_CLKSTCTRL Register Field Descriptions
  554
- CM_PER_CPGMAC0_CLKCTRL Register
  555
- CM_PER_CPGMAC0_CLKCTRL Register Field Descriptions
  555
- CM_PER_LCDC_CLKCTRL Register
  556
- CM_PER_LCDC_CLKCTRL Register Field Descriptions
  556
- CM_PER_USB0_CLKCTRL Register
  557
- CM_PER_USB0_CLKCTRL Register Field Descriptions
  557
- CM_PER_TPTC0_CLKCTRL Register
  558
- CM_PER_TPTC0_CLKCTRL Register Field Descriptions
  558
- CM_PER_EMIF_CLKCTRL Register
  559
- CM_PER_EMIF_CLKCTRL Register Field Descriptions
  559
- CM_PER_OCMCRAM_CLKCTRL Register
  560
- CM_PER_OCMCRAM_CLKCTRL Register Field Descriptions
  560
- CM_PER_GPMC_CLKCTRL Register
  561
- CM_PER_GPMC_CLKCTRL Register Field Descriptions
  561
- CM_PER_MCASP0_CLKCTRL Register
  562
- CM_PER_MCASP0_CLKCTRL Register Field Descriptions
  562
- CM_PER_UART5_CLKCTRL Register
  563
- CM_PER_UART5_CLKCTRL Register Field Descriptions
  563
- CM_PER_MMC0_CLKCTRL Register
  564
- CM_PER_MMC0_CLKCTRL Register Field Descriptions
  564
- CM_PER_ELM_CLKCTRL Register
  565
- CM_PER_ELM_CLKCTRL Register Field Descriptions
  565
- CM_PER_I2C2_CLKCTRL Register
  566
- CM_PER_I2C2_CLKCTRL Register Field Descriptions
  566
- CM_PER_I2C1_CLKCTRL Register
  567
- CM_PER_I2C1_CLKCTRL Register Field Descriptions
  567
- CM_PER_SPI0_CLKCTRL Register
  568
- CM_PER_SPI0_CLKCTRL Register Field Descriptions
  568
- CM_PER_SPI1_CLKCTRL Register
  569
- CM_PER_SPI1_CLKCTRL Register Field Descriptions
  569
- CM_PER_L4LS_CLKCTRL Register
  570
- CM_PER_L4LS_CLKCTRL Register Field Descriptions
  570
- CM_PER_L4FW_CLKCTRL Register
  571
- CM_PER_L4FW_CLKCTRL Register Field Descriptions
  571
- CM_PER_MCASP1_CLKCTRL Register
  572
- CM_PER_MCASP1_CLKCTRL Register Field Descriptions
  572
- CM_PER_UART1_CLKCTRL Register
  573
- CM_PER_UART1_CLKCTRL Register Field Descriptions
  573
- CM_PER_UART2_CLKCTRL Register
  574
- CM_PER_UART2_CLKCTRL Register Field Descriptions
  574
- CM_PER_UART3_CLKCTRL Register
  575
- CM_PER_UART3_CLKCTRL Register Field Descriptions
  575
- CM_PER_UART4_CLKCTRL Register
  576
- CM_PER_UART4_CLKCTRL Register Field Descriptions
  576
- CM_PER_TIMER7_CLKCTRL Register
  577
- CM_PER_TIMER7_CLKCTRL Register Field Descriptions
  577
- CM_PER_TIMER2_CLKCTRL Register
  578
- CM_PER_TIMER2_CLKCTRL Register Field Descriptions
  578
- CM_PER_TIMER3_CLKCTRL Register
  579
- CM_PER_TIMER3_CLKCTRL Register Field Descriptions
  579
- CM_PER_TIMER4_CLKCTRL Register
  580
- CM_PER_TIMER4_CLKCTRL Register Field Descriptions
  580
- CM_PER_GPIO1_CLKCTRL Register
  581
- CM_PER_GPIO1_CLKCTRL Register Field Descriptions
  581
- CM_PER_GPIO2_CLKCTRL Register
  582
- CM_PER_GPIO2_CLKCTRL Register Field Descriptions
  582
- CM_PER_GPIO3_CLKCTRL Register
  583
- CM_PER_GPIO3_CLKCTRL Register Field Descriptions
  583
- CM_PER_TPCC_CLKCTRL Register
  584
- CM_PER_TPCC_CLKCTRL Register Field Descriptions
  584
- CM_PER_DCAN0_CLKCTRL Register
  585
- CM_PER_DCAN0_CLKCTRL Register Field Descriptions
  585
- CM_PER_DCAN1_CLKCTRL Register
  586
- CM_PER_DCAN1_CLKCTRL Register Field Descriptions
  586
- CM_PER_EPWMSS1_CLKCTRL Register
  587
- CM_PER_EPWMSS1_CLKCTRL Register Field Descriptions
  587
- CM_PER_EMIF_FW_CLKCTRL Register
  588
- CM_PER_EMIF_FW_CLKCTRL Register Field Descriptions
  588
- CM_PER_EPWMSS0_CLKCTRL Register
  589
- CM_PER_EPWMSS0_CLKCTRL Register Field Descriptions
  589
- CM_PER_EPWMSS2_CLKCTRL Register
  590
- CM_PER_EPWMSS2_CLKCTRL Register Field Descriptions
  590
- CM_PER_L3_INSTR_CLKCTRL Register
  591
- CM_PER_L3_INSTR_CLKCTRL Register Field Descriptions
  591
- CM_PER_L3_CLKCTRL Register
  592
- CM_PER_L3_CLKCTRL Register Field Descriptions
  592
- CM_PER_IEEE5000_CLKCTRL Register
  593
- CM_PER_IEEE5000_CLKCTRL Register Field Descriptions
  593
- CM_PER_PRU_ICSS_CLKCTRL Register
  594
- CM_PER_PRU_ICSS_CLKCTRL Register Field Descriptions
  594
- CM_PER_TIMER5_CLKCTRL Register
  595
- CM_PER_TIMER5_CLKCTRL Register Field Descriptions
  595
- CM_PER_TIMER6_CLKCTRL Register
  596
- CM_PER_TIMER6_CLKCTRL Register Field Descriptions
  596
- CM_PER_MMC1_CLKCTRL Register
  597
- CM_PER_MMC1_CLKCTRL Register Field Descriptions
  597
- CM_PER_MMC2_CLKCTRL Register
  598
- CM_PER_MMC2_CLKCTRL Register Field Descriptions
  598
- CM_PER_TPTC1_CLKCTRL Register
  599
- CM_PER_TPTC1_CLKCTRL Register Field Descriptions
  599
- CM_PER_TPTC2_CLKCTRL Register
  600
- CM_PER_TPTC2_CLKCTRL Register Field Descriptions
  600
- CM_PER_SPINLOCK_CLKCTRL Register
  601
- CM_PER_SPINLOCK_CLKCTRL Register Field Descriptions
  601
- CM_PER_MAILBOX0_CLKCTRL Register
  602
- CM_PER_MAILBOX0_CLKCTRL Register Field Descriptions
  602
- CM_PER_L4HS_CLKSTCTRL Register
  603
- CM_PER_L4HS_CLKSTCTRL Register Field Descriptions
  603
- CM_PER_L4HS_CLKCTRL Register
  604
- CM_PER_L4HS_CLKCTRL Register Field Descriptions
  604
- CM_PER_OCPWP_L3_CLKSTCTRL Register
  605
- CM_PER_OCPWP_L3_CLKSTCTRL Register Field Descriptions
  605
- CM_PER_OCPWP_CLKCTRL Register
  606
- CM_PER_OCPWP_CLKCTRL Register Field Descriptions
  606
- CM_PER_PRU_ICSS_CLKSTCTRL Register
  607
- CM_PER_PRU_ICSS_CLKSTCTRL Register Field Descriptions
  607
- CM_PER_CPSW_CLKSTCTRL Register
  608
- CM_PER_CPSW_CLKSTCTRL Register Field Descriptions
  608
- CM_PER_LCDC_CLKSTCTRL Register
  609
- CM_PER_LCDC_CLKSTCTRL Register Field Descriptions
  609
- CM_PER_CLKDIV32K_CLKCTRL Register
  610
- CM_PER_CLKDIV32K_CLKCTRL Register Field Descriptions
  610
- CM_PER_CLK_24MHZ_CLKSTCTRL Register
  611
- CM_PER_CLK_24MHZ_CLKSTCTRL Register Field Descriptions
  611
- Cm_Wkup Registers
  611
- CM_WKUP_CLKSTCTRL Register
  615
- CM_WKUP_CLKSTCTRL Register Field Descriptions
  615
- CM_WKUP_CONTROL_CLKCTRL Register
  617
- CM_WKUP_CONTROL_CLKCTRL Register Field Descriptions
  617
- CM_WKUP_GPIO0_CLKCTRL Register
  618
- CM_WKUP_GPIO0_CLKCTRL Register Field Descriptions
  618
- CM_WKUP_L4WKUP_CLKCTRL Register
  619
- CM_WKUP_L4WKUP_CLKCTRL Register Field Descriptions
  619
- CM_WKUP_TIMER0_CLKCTRL Register
  620
- CM_WKUP_TIMER0_CLKCTRL Register Field Descriptions
  620
- CM_WKUP_DEBUGSS_CLKCTRL Register
  621
- CM_WKUP_DEBUGSS_CLKCTRL Register Field Descriptions
  621
- CM_L3_AON_CLKSTCTRL Register
  622
- CM_L3_AON_CLKSTCTRL Register Field Descriptions
  622
- CM_AUTOIDLE_DPLL_MPU Register
  623
- CM_IDLEST_DPLL_MPU Register
  624
- CM_SSC_DELTAMSTEP_DPLL_MPU Register
  625
- CM_SSC_MODFREQDIV_DPLL_MPU Register
  626
- CM_CLKSEL_DPLL_MPU Register
  627
- CM_AUTOIDLE_DPLL_DDR Register
  628
- CM_IDLEST_DPLL_DDR Register
  629
- CM_SSC_DELTAMSTEP_DPLL_DDR Register
  630
- CM_SSC_MODFREQDIV_DPLL_DDR Register
  631
- CM_CLKSEL_DPLL_DDR Register
  632
- CM_AUTOIDLE_DPLL_DISP Register
  633
- CM_AUTOIDLE_DPLL_DISP Register Field Descriptions
  633
- CM_IDLEST_DPLL_DISP Register
  634
- CM_IDLEST_DPLL_DISP Register Field Descriptions
  634
- CM_SSC_DELTAMSTEP_DPLL_DISP Register
  635
- CM_SSC_DELTAMSTEP_DPLL_DISP Register Field Descriptions
  635
- CM_SSC_MODFREQDIV_DPLL_DISP Register
  636
- CM_SSC_MODFREQDIV_DPLL_DISP Register Field Descriptions
  636
- CM_CLKSEL_DPLL_DISP Register
  637
- CM_CLKSEL_DPLL_DISP Register Field Descriptions
  637
- CM_AUTOIDLE_DPLL_CORE Register
  638
- CM_AUTOIDLE_DPLL_CORE Register Field Descriptions
  638
- CM_IDLEST_DPLL_CORE Register
  639
- CM_IDLEST_DPLL_CORE Register Field Descriptions
  639
- CM_SSC_DELTAMSTEP_DPLL_CORE Register
  640
- CM_SSC_DELTAMSTEP_DPLL_CORE Register Field Descriptions
  640
- CM_SSC_MODFREQDIV_DPLL_CORE Register
  641
- CM_SSC_MODFREQDIV_DPLL_CORE Register Field Descriptions
  641
- CM_CLKSEL_DPLL_CORE Register
  642
- CM_CLKSEL_DPLL_CORE Register Field Descriptions
  642
- CM_AUTOIDLE_DPLL_PER Register
  643
- CM_IDLEST_DPLL_PER Register
  644
- CM_SSC_DELTAMSTEP_DPLL_PER Register
  645
- CM_SSC_MODFREQDIV_DPLL_PER Register
  646
- CM_CLKDCOLDO_DPLL_PER Register
  647
- CM_DIV_M4_DPLL_CORE Register
  648
- CM_DIV_M4_DPLL_CORE Register Field Descriptions
  648
- CM_DIV_M5_DPLL_CORE Register
  649
- CM_DIV_M5_DPLL_CORE Register Field Descriptions
  649
- CM_CLKMODE_DPLL_MPU Register
  650
- CM_CLKMODE_DPLL_MPU Register Field Descriptions
  651
- CM_CLKMODE_DPLL_PER Register
  652
- CM_CLKMODE_DPLL_CORE Register
  653
- CM_CLKMODE_DPLL_CORE Register Field Descriptions
  653
- CM_CLKMODE_DPLL_DDR Register
  655
- CM_CLKMODE_DPLL_DDR Register Field Descriptions
  656
- CM_CLKMODE_DPLL_DISP Register
  657
- CM_CLKMODE_DPLL_DISP Register Field Descriptions
  657
- CM_CLKSEL_DPLL_PERIPH Register
  659
- CM_CLKSEL_DPLL_PERIPH Register Field Descriptions
  659
- CM_DIV_M2_DPLL_DDR Register
  660
- CM_DIV_M2_DPLL_DISP Register
  661
- CM_DIV_M2_DPLL_DISP Register Field Descriptions
  661
- CM_DIV_M2_DPLL_MPU Register
  662
- CM_DIV_M2_DPLL_PER Register
  663
- CM_WKUP_WKUP_M3_CLKCTRL Register
  664
- CM_WKUP_WKUP_M3_CLKCTRL Register Field Descriptions
  664
- CM_WKUP_UART0_CLKCTRL Register
  665
- CM_WKUP_UART0_CLKCTRL Register Field Descriptions
  665
- CM_WKUP_I2C0_CLKCTRL Register
  666
- CM_WKUP_I2C0_CLKCTRL Register Field Descriptions
  666
- CM_WKUP_ADC_TSC_CLKCTRL Register
  667
- CM_WKUP_ADC_TSC_CLKCTRL Register Field Descriptions
  667
- CM_WKUP_SMARTREFLEX0_CLKCTRL Register
  668
- CM_WKUP_SMARTREFLEX0_CLKCTRL Register Field Descriptions
  668
- CM_WKUP_TIMER1_CLKCTRL Register
  669
- CM_WKUP_TIMER1_CLKCTRL Register Field Descriptions
  669
- CM_WKUP_SMARTREFLEX1_CLKCTRL Register
  670
- CM_WKUP_SMARTREFLEX1_CLKCTRL Register Field Descriptions
  670
- CM_L4_WKUP_AON_CLKSTCTRL Register
  671
- CM_L4_WKUP_AON_CLKSTCTRL Register Field Descriptions
  671
- CM_WKUP_WDT1_CLKCTRL Register
  672
- CM_WKUP_WDT1_CLKCTRL Register Field Descriptions
  672
- CM_DIV_M6_DPLL_CORE Register
  673
- CM_DIV_M6_DPLL_CORE Register Field Descriptions
  673
- Cm_Dpll Registers
  674
- CLKSEL_TIMER7_CLK Register
  675
- CLKSEL_TIMER2_CLK Register
  676
- CLKSEL_TIMER3_CLK Register
  677
- CLKSEL_TIMER4_CLK Register
  678
- CM_MAC_CLKSEL Register
  679
- CM_MAC_CLKSEL Register Field Descriptions
  679
- CLKSEL_TIMER5_CLK Register
  680
- CLKSEL_TIMER6_CLK Register
  681
- CM_CPTS_RFT_CLKSEL Register
  682
- CM_CPTS_RFT_CLKSEL Register Field Descriptions
  682
- CLKSEL_TIMER1MS_CLK Register
  683
- CLKSEL_TIMER1MS_CLK Register Field Descriptions
  683
- CLKSEL_GFX_FCLK Register
  684
- CLKSEL_GFX_FCLK Register Field Descriptions
  684
- CLKSEL_PRU_ICSS_OCP_CLK Register
  685
- CLKSEL_LCDC_PIXEL_CLK Register
  686
- CLKSEL_WDT1_CLK Register
  687
- CLKSEL_GPIO0_DBCLK Register
  688
- CLKSEL_GPIO0_DBCLK Register Field Descriptions
  688
- Cm_Mpu Registers
  688
- CM_MPU_CLKSTCTRL Register
  689
- CM_MPU_CLKSTCTRL Register Field Descriptions
  689
- Cm_Device Registers
  690
- CM_MPU_MPU_CLKCTRL Register
  690
- CM_MPU_MPU_CLKCTRL Register Field Descriptions
  690
- CM_CLKOUT_CTRL Register
  692
- CM_CLKOUT_CTRL Register Field Descriptions
  692
- Cm_Rtc Registers
  693
- CM_RTC_RTC_CLKCTRL Register
  694
- CM_RTC_RTC_CLKCTRL Register Field Descriptions
  694
- CM_RTC_CLKSTCTRL Register
  695
- CM_RTC_CLKSTCTRL Register Field Descriptions
  695
- Cm_Gfx Registers
  696
- CM_GFX_L3_CLKSTCTRL Register
  697
- CM_GFX_L3_CLKSTCTRL Register Field Descriptions
  697
- CM_GFX_GFX_CLKCTRL Register
  698
- CM_GFX_GFX_CLKCTRL Register Field Descriptions
  698
- CM_GFX_L4LS_GFX_CLKSTCTRL Register
  699
- CM_GFX_L4LS_GFX_CLKSTCTRL Register Field Descriptions
  699
- CM_GFX_MMUCFG_CLKCTRL Register
  700
- CM_GFX_MMUCFG_CLKCTRL Register Field Descriptions
  700
- Cm_Cefuse Registers
  701
- CM_GFX_MMUDATA_CLKCTRL Register
  701
- CM_GFX_MMUDATA_CLKCTRL Register Field Descriptions
  701
- CM_CEFUSE_CLKSTCTRL Register
  703
- CM_CEFUSE_CLKSTCTRL Register Field Descriptions
  703
- CM_CEFUSE_CEFUSE_CLKCTRL Register
  704
- CM_CEFUSE_CEFUSE_CLKCTRL Register Field Descriptions
  704
- Prm_Irq Registers
  705
- REVISION_PRM Register
  706
- PRM_IRQSTATUS_MPU Register
  707
- PRM_IRQENABLE_MPU Register
  708
- PRM_IRQSTATUS_M3 Register
  709
- PRM_IRQENABLE_M3 Register
  710
- Prm_Per Registers
  711
- RM_PER_RSTCTRL Register
  712
- RM_PER_RSTCTRL Register Field Descriptions
  712
- PM_PER_PWRSTST Register
  713
- PM_PER_PWRSTST Register Field Descriptions
  713
- PM_PER_PWRSTCTRL Register
  714
- PM_PER_PWRSTCTRL Register Field Descriptions
  714
- Prm_Wkup Registers
  715
- RM_WKUP_RSTCTRL Register
  716
- RM_WKUP_RSTCTRL Register Field Descriptions
  716
- PM_WKUP_PWRSTCTRL Register
  717
- PM_WKUP_PWRSTCTRL Register Field Descriptions
  717
- PM_WKUP_PWRSTST Register
  718
- PM_WKUP_PWRSTST Register Field Descriptions
  718
- Prm_Mpu Registers
  719
- RM_WKUP_RSTST Register
  719
- RM_WKUP_RSTST Register Field Descriptions
  719
- PM_MPU_PWRSTCTRL Register
  721
- PM_MPU_PWRSTCTRL Register Field Descriptions
  721
- PM_MPU_PWRSTST Register
  723
- PM_MPU_PWRSTST Register Field Descriptions
  723
- Prm_Device Registers
  724
- RM_MPU_RSTST Register
  724
- RM_MPU_RSTST Register Field Descriptions
  724
- PRM_RSTCTRL Register
  726
- PRM_RSTCTRL Register Field Descriptions
  726
- PRM_RSTTIME Register
  727
- PRM_RSTTIME Register Field Descriptions
  727
- PRM_RSTST Register
  728
- PRM_RSTST Register Field Descriptions
  728
- PRM_SRAM_COUNT Register
  729
- PRM_SRAM_COUNT Register Field Descriptions
  729
- PRM_LDO_SRAM_CORE_SETUP Register
  730
- PRM_LDO_SRAM_CORE_SETUP Register Field Descriptions
  730
- PRM_LDO_SRAM_CORE_CTRL Register
  732
- PRM_LDO_SRAM_CORE_CTRL Register Field Descriptions
  732
- PRM_LDO_SRAM_MPU_SETUP Register
  733
- PRM_LDO_SRAM_MPU_SETUP Register Field Descriptions
  733
- PRM_LDO_SRAM_MPU_CTRL Register
  735
- PRM_LDO_SRAM_MPU_CTRL Register Field Descriptions
  735
- Prm_Rtc Registers
  735
- PM_RTC_PWRSTCTRL Register
  737
- PM_RTC_PWRSTCTRL Register Field Descriptions
  737
- PM_RTC_PWRSTST Register
  738
- PM_RTC_PWRSTST Register Field Descriptions
  738
- Prm_Gfx Registers
  738
- PM_GFX_PWRSTCTRL Register
  740
- PM_GFX_PWRSTCTRL Register Field Descriptions
  740
- RM_GFX_RSTCTRL Register
  741
- RM_GFX_RSTCTRL Register Field Descriptions
  741
- PM_GFX_PWRSTST Register
  742
- PM_GFX_PWRSTST Register Field Descriptions
  742
- Prm_Cefuse Registers
  743
- RM_GFX_RSTST Register
  743
- RM_GFX_RSTST Register Field Descriptions
  743
- PM_CEFUSE_PWRSTCTRL Register
  744
- PM_CEFUSE_PWRSTCTRL Register Field Descriptions
  744
- PM_CEFUSE_PWRSTST Register
  745
- PM_CEFUSE_PWRSTST Register Field Descriptions
  745
- Pad Control Register Field Descriptions
  747
- Mode Selection
  748
- Pull Selection
  748
- Event Crossbar
  749
- Interconnect Priority Values
  750
- USB Charger Detection
  751
- Gmii_Sel Register
  752
- Available Sources for Timer[5-7] and Ecap[0-2] Events
  753
- Selection Mux Values
  755
- Timer Events
  755
- DDR Impedance Control Settings
  756
- DDR PHY to IO Pin Mapping
  756
- DDR Slew Rate Control Settings
  756
- Control_Module Registers
  757
- Control_Revision Register
  762
- Control_Revision Register Field Descriptions
  762
- Control_Hwinfo Register
  763
- Control_Hwinfo Register Field Descriptions
  763
- Control_Sysconfig Register
  764
- Control_Sysconfig Register Field Descriptions
  764
- Control_Status Register
  765
- Control_Status Register Field Descriptions
  765
- Control_Emif_Sdram_Config Register
  766
- Control_Emif_Sdram_Config Register Field Descriptions
  766
- Core_Sldo_Ctrl Register
  768
- Core_Sldo_Ctrl Register Field Descriptions
  768
- Mpu_Sldo_Ctrl Register
  769
- Mpu_Sldo_Ctrl Register Field Descriptions
  769
- Clk32Kdivratio_Ctrl Register
  770
- Clk32Kdivratio_Ctrl Register Field Descriptions
  770
- Bandgap_Ctrl Register
  771
- Bandgap_Ctrl Register Field Descriptions
  771
- Bandgap_Trim Register
  772
- Bandgap_Trim Register Field Descriptions
  772
- Pll_Clkinpulow_Ctrl Register
  773
- Pll_Clkinpulow_Ctrl Register Field Descriptions
  773
- Mosc_Ctrl Register
  774
- Mosc_Ctrl Register Field Descriptions
  774
- Deepsleep_Ctrl Register
  775
- Deepsleep_Ctrl Register Field Descriptions
  775
- Dpll_Pwr_Sw_Status Register
  776
- Dpll_Pwr_Sw_Status Register Field Descriptions
  776
- Device_Id Register
  777
- Device_Id Register Field Descriptions
  777
- Dev_Feature Register
  778
- Dev_Feature Register Field Descriptions
  778
- Init_Priority_0 Register
  779
- Init_Priority_0 Register Field Descriptions
  779
- Init_Priority_1 Register
  780
- Init_Priority_1 Register Field Descriptions
  780
- Mmu_Cfg Register
  781
- Mmu_Cfg Register Field Descriptions
  781
- Tptc_Cfg Register
  782
- Tptc_Cfg Register Field Descriptions
  782
- Usb_Ctrl0 Register
  783
- Usb_Ctrl0 Register Field Descriptions
  783
- Usb_Sts0 Register
  785
- Usb_Sts0 Register Field Descriptions
  785
- Usb_Ctrl1 Register
  786
- Usb_Ctrl1 Register Field Descriptions
  786
- Usb_Sts1 Register
  788
- Usb_Sts1 Register Field Descriptions
  788
- Mac_Id0_Lo Register
  789
- Mac_Id0_Lo Register Field Descriptions
  789
- Mac_Id0_Hi Register
  790
- Mac_Id0_Hi Register Field Descriptions
  790
- Mac_Id1_Lo Register
  791
- Mac_Id1_Lo Register Field Descriptions
  791
- Mac_Id1_Hi Register
  792
- Mac_Id1_Hi Register Field Descriptions
  792
- Dcan_Raminit Register
  793
- Dcan_Raminit Register Field Descriptions
  793
- Usb_Wkup_Ctrl Register
  794
- Usb_Wkup_Ctrl Register Field Descriptions
  794
- Gmii_Sel Register Field Descriptions
  795
- Pwmss_Ctrl Register
  796
- Pwmss_Ctrl Register Field Descriptions
  796
- Mreqprio_0 Register
  797
- Mreqprio_0 Register Field Descriptions
  797
- Mreqprio_1 Register
  798
- Mreqprio_1 Register Field Descriptions
  798
- Hw_Event_Sel_Grp1 Register
  799
- Hw_Event_Sel_Grp1 Register Field Descriptions
  799
- Hw_Event_Sel_Grp2 Register
  800
- Hw_Event_Sel_Grp2 Register Field Descriptions
  800
- Hw_Event_Sel_Grp3 Register
  801
- Hw_Event_Sel_Grp3 Register Field Descriptions
  801
- Hw_Event_Sel_Grp4 Register
  802
- Hw_Event_Sel_Grp4 Register Field Descriptions
  802
- Smrt_Ctrl Register
  803
- Smrt_Ctrl Register Field Descriptions
  803
- Mpuss_Hw_Debug_Sel Register
  804
- Mpuss_Hw_Debug_Sel Register Field Descriptions
  804
- Mpuss_Hw_Dbg_Info Register
  805
- Mpuss_Hw_Dbg_Info Register Field Descriptions
  805
- Vdd_Mpu_Opp_050 Register
  806
- Vdd_Mpu_Opp_050 Register Field Descriptions
  806
- Vdd_Mpu_Opp_100 Register
  807
- Vdd_Mpu_Opp_100 Register Field Descriptions
  807
- Vdd_Mpu_Opp_120 Register
  808
- Vdd_Mpu_Opp_120 Register Field Descriptions
  808
- Vdd_Mpu_Opp_Turbo Register
  809
- Vdd_Mpu_Opp_Turbo Register Field Descriptions
  809
- Vdd_Core_Opp_050 Register
  810
- Vdd_Core_Opp_050 Register Field Descriptions
  810
- Vdd_Core_Opp_100 Register
  811
- Vdd_Core_Opp_100 Register Field Descriptions
  811
- Bb_Scale Register
  812
- Bb_Scale Register Field Descriptions
  812
- Usb_Vid_Pid Register
  813
- Usb_Vid_Pid Register Field Descriptions
  813
- Efuse_Sma Register
  814
- Efuse_Sma Register Field Descriptions
  814
- Conf_<Module>_<Pin> Register
  815
- Conf_<Module>_<Pin> Register Field Descriptions
  815
- Cqdetect_Status Register
  816
- Cqdetect_Status Register Field Descriptions
  816
- Ddr_Io_Ctrl Register
  817
- Ddr_Io_Ctrl Register Field Descriptions
  817
- Vtp_Ctrl Register
  818
- Vtp_Ctrl Register Field Descriptions
  818
- Vref_Ctrl Register
  819
- Vref_Ctrl Register Field Descriptions
  819
- Tpcc_Evt_Mux_0_3 Register
  820
- Tpcc_Evt_Mux_0_3 Register Field Descriptions
  820
- Tpcc_Evt_Mux_4_7 Register
  821
- Tpcc_Evt_Mux_4_7 Register Field Descriptions
  821
- Tpcc_Evt_Mux_8_11 Register
  822
- Tpcc_Evt_Mux_8_11 Register Field Descriptions
  822
- Tpcc_Evt_Mux_12_15 Register
  823
- Tpcc_Evt_Mux_12_15 Register Field Descriptions
  823
- Tpcc_Evt_Mux_16_19 Register
  824
- Tpcc_Evt_Mux_16_19 Register Field Descriptions
  824
- Tpcc_Evt_Mux_20_23 Register
  825
- Tpcc_Evt_Mux_20_23 Register Field Descriptions
  825
- Tpcc_Evt_Mux_24_27 Register
  826
- Tpcc_Evt_Mux_24_27 Register Field Descriptions
  826
- Tpcc_Evt_Mux_28_31 Register
  827
- Tpcc_Evt_Mux_28_31 Register Field Descriptions
  827
- Tpcc_Evt_Mux_32_35 Register
  828
- Tpcc_Evt_Mux_32_35 Register Field Descriptions
  828
- Tpcc_Evt_Mux_36_39 Register
  829
- Tpcc_Evt_Mux_36_39 Register Field Descriptions
  829
- Tpcc_Evt_Mux_40_43 Register
  830
- Tpcc_Evt_Mux_40_43 Register Field Descriptions
  830
- Tpcc_Evt_Mux_44_47 Register
  831
- Tpcc_Evt_Mux_44_47 Register Field Descriptions
  831
- Tpcc_Evt_Mux_48_51 Register
  832
- Tpcc_Evt_Mux_48_51 Register Field Descriptions
  832
- Tpcc_Evt_Mux_52_55 Register
  833
- Tpcc_Evt_Mux_52_55 Register Field Descriptions
  833
- Tpcc_Evt_Mux_56_59 Register
  834
- Tpcc_Evt_Mux_56_59 Register Field Descriptions
  834
- Tpcc_Evt_Mux_60_63 Register
  835
- Tpcc_Evt_Mux_60_63 Register Field Descriptions
  835
- Timer_Evt_Capt Register
  836
- Timer_Evt_Capt Register Field Descriptions
  836
- Ecap_Evt_Capt Register
  837
- Ecap_Evt_Capt Register Field Descriptions
  837
- Adc_Evt_Capt Register
  838
- Adc_Evt_Capt Register Field Descriptions
  838
- Reset_Iso Register
  839
- Reset_Iso Register Field Descriptions
  839
- Dpll_Pwr_Sw_Ctrl Register
  840
- Dpll_Pwr_Sw_Ctrl Register Field Descriptions
  840
- Ddr_Cke_Ctrl Register
  842
- Ddr_Cke_Ctrl Register Field Descriptions
  842
- Sma2 Register
  843
- Sma2 Register Field Descriptions
  843
- M3_Txev_Eoi Register
  844
- M3_Txev_Eoi Register Field Descriptions
  844
- Ipc_Msg_Reg0 Register
  845
- Ipc_Msg_Reg0 Register Field Descriptions
  845
- Ipc_Msg_Reg1 Register
  846
- Ipc_Msg_Reg1 Register Field Descriptions
  846
- Ipc_Msg_Reg2 Register
  847
- Ipc_Msg_Reg2 Register Field Descriptions
  847
- Ipc_Msg_Reg3 Register
  848
- Ipc_Msg_Reg3 Register Field Descriptions
  848
- Ipc_Msg_Reg4 Register
  849
- Ipc_Msg_Reg4 Register Field Descriptions
  849
- Ipc_Msg_Reg5 Register
  850
- Ipc_Msg_Reg5 Register Field Descriptions
  850
- Ipc_Msg_Reg6 Register
  851
- Ipc_Msg_Reg6 Register Field Descriptions
  851
- Ipc_Msg_Reg7 Register
  852
- Ipc_Msg_Reg7 Register Field Descriptions
  852
- Ddr_Cmd0_Ioctrl Register
  853
- Ddr_Cmd0_Ioctrl Register Field Descriptions
  853
- Ddr_Cmd1_Ioctrl Register
  855
- Ddr_Cmd1_Ioctrl Register Field Descriptions
  855
- Ddr_Cmd2_Ioctrl Register
  857
- Ddr_Cmd2_Ioctrl Register Field Descriptions
  857
- Ddr_Data0_Ioctrl Register
  859
- Ddr_Data0_Ioctrl Register Field Descriptions
  859
- Ddr_Data1_Ioctrl Register
  861
- Ddr_Data1_Ioctrl Register Field Descriptions
  861
- L3 Topology
  865
- L3 Master - Slave Connectivity
  866
- Mconnid Assignment
  867
- L4 Topology
  868
- EDMA3 Controller Block Diagram
  870
- TPCC Clock Signals
  873
- TPCC Connectivity Attributes
  873
- TPCC Integration
  873
- TPTC Clock Signals
  874
- TPTC Connectivity Attributes
  874
- TPTC Integration
  874
- EDMA3 Channel Controller (EDMA3CC) Block Diagram
  877
- EDMA3 Transfer Controller (EDMA3TC) Block Diagram
  878
- Definition of ACNT, BCNT, and CCNT
  879
- A-Synchronized Transfers (ACNT = N, BCNT = 4, CCNT = 3)
  880
- AB-Synchronized Transfers (ACNT = N, BCNT = 4, CCNT = 3)
  881
- EDMA3 Parameter RAM Contents
  882
- Param Set
  883
- EDMA3 Channel Parameter Description
  884
- Channel Options Parameter (OPT)
  885
- Channel Options Parameters (OPT) Field Descriptions
  885
- Dummy and Null Transfer Request
  889
- Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy Param Set)
  890
- Linked Transfer
  892
- Link-To-Self Transfer
  893
- Expected Number of Transfers for Non-Null Transfer
  896
- DMA Channel and QDMA Channel to Param Mapping
  898
- QDMA Channel to Param Mapping
  899
- Shadow Region Registers
  900
- Chain Event Triggers
  902
- EDMA3 Error Interrupts
  902
- EDMA3 Transfer Completion Interrupts
  902
- Number of Interrupts
  903
- Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping
  903
- Interrupt Diagram
  904
- Error Interrupt Operation
  907
- Allowed Accesses
  908
- MPPA Registers to Region Assignment
  908
- Example Access Allowed
  909
- Example Access Denied
  909
- Channel Options Parameter (OPT) Example
  911
- Param Set Content for Proxy Memory Protection Example
  911
- Proxy Memory Protection Example
  912
- Read/Write Command Optimization Rules
  914
- EDMA3 Transfer Controller Configurations
  916
- EDMA3 Prioritization
  919
- Block Move Example
  920
- Block Move Example Param Configuration
  920
- Subframe Extraction Example
  921
- Subframe Extraction Example Param Configuration
  921
- Data Sorting Example
  922
- Data Sorting Example Param Configuration
  923
- Servicing Incoming Mcasp Data Example
  924
- Servicing Peripheral Burst Example
  925
- Servicing Peripheral Burst Example Param Configuration
  926
- Servicing Continuous Mcasp Data Example
  927
- Servicing Continuous Mcasp Data Example Param Configuration
  928
- Servicing Continuous Mcasp Data Example Reload Param Configuration
  929
- Ping-Pong Buffering for Mcasp Data Example
  931
- Ping-Pong Buffering for Mcasp Example Param Configuration
  931
- Ping-Pong Buffering for Mcasp Example Pong Param Configuration
  932
- Ping-Pong Buffering for Mcasp Example Ping Param Configuration
  933
- Intermediate Transfer Completion Chaining Example
  934
- Single Large Block Transfer Example
  935
- Smaller Packet Data Transfers Example
  935
- Direct Mapped
  936
- Crossbar Mapped
  937
- EDMACC Registers
  939
- Peripheral ID Register (PID)
  942
- Peripheral ID Register (PID) Field Descriptions
  942
- EDMA3CC Configuration Register (CCCFG)
  943
- EDMA3CC Configuration Register (CCCFG) Field Descriptions
  943
- EDMA3CC System Configuration Register (SYSCONFIG)
  945
- EDMA3CC System Configuration Register (SYSCONFIG) Field Descriptions
  945
- DMA Channel Map N Registers (Dchmapn)
  946
- DMA Channel Map N Registers (Dchmapn) Field Descriptions
  946
- QDMA Channel Map N Registers (Qchmapn)
  947
- QDMA Channel Map N Registers (Qchmapn) Field Descriptions
  947
- Bits in Dmaqnumn
  948
- DMA Channel Queue N Number Registers (Dmaqnumn)
  948
- DMA Channel Queue N Number Registers (Dmaqnumn) Field Descriptions
  948
- QDMA Channel Queue Number Register (QDMAQNUM)
  949
- QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions
  949
- Queue Priority Register (QUEPRI)
  950
- Queue Priority Register (QUEPRI) Field Descriptions
  950
- Event Missed Register (EMR)
  951
- Event Missed Register (EMR) Field Descriptions
  951
- Event Missed Register High (EMRH)
  951
- Event Missed Clear Register (EMCR)
  952
- Event Missed Clear Register (EMCR) Field Descriptions
  952
- Event Missed Clear Register High (EMCRH)
  952
- Event Missed Clear Register High (EMCRH) Field Descriptions
  952
- QDMA Event Missed Register (QEMR)
  953
- QDMA Event Missed Register (QEMR) Field Descriptions
  953
- EDMA3CC Error Register (CCERR)
  954
- QDMA Event Missed Clear Register (QEMCR)
  954
- QDMA Event Missed Clear Register (QEMCR) Field Descriptions
  954
- EDMA3CC Error Clear Register (CCERRCLR)
  955
- EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions
  955
- EDMA3CC Error Register (CCERR) Field Descriptions
  955
- Error Evaluation Register (EEVAL)
  957
- Error Evaluation Register (EEVAL) Field Descriptions
  957
- DMA Region Access Enable High Register for Region M (Draehm)
  958
- DMA Region Access Enable Register for Region M (Draem)
  958
- DMA Region Access Enable Registers for Region M (Draem/Draehm) Field Descriptions
  958
- Field Descriptions
  958
- QDMA Region Access Enable for Region M (Qraem) Field Descriptions
  959
- QDMA Region Access Enable for Region M (Qraem)32-Bit, 2 Rows
  959
- Event Queue Entry Registers (Qxey)
  960
- Event Queue Entry Registers (Qxey) Field Descriptions
  960
- Queue Status Register N (Qstatn)
  961
- Queue Status Register N (Qstatn) Field Descriptions
  961
- Queue Watermark Threshold a Register (QWMTHRA)
  962
- Queue Watermark Threshold a Register (QWMTHRA) Field Descriptions
  962
- EDMA3CC Status Register (CCSTAT)
  963
- EDMA3CC Status Register (CCSTAT) Field Descriptions
  963
- Memory Protection Fault Address Register (MPFAR)
  965
- Memory Protection Fault Address Register (MPFAR) Field Descriptions
  965
- Memory Protection Fault Status Register (MPFSR)
  966
- Memory Protection Fault Status Register (MPFSR) Field Descriptions
  966
- Memory Protection Fault Command Register (MPFCR)
  967
- Memory Protection Fault Command Register (MPFCR) Field Descriptions
  967
- Memory Protection Page Attribute Register (Mppan)
  968
- Memory Protection Page Attribute Register (Mppan) Field Descriptions
  968
- Event Register (ER)
  970
- Event Register (ER) Field Descriptions
  970
- Event Register High (ERH)
  970
- Event Clear Register (ECR)
  971
- Event Clear Register (ECR) Field Descriptions
  971
- Event Clear Register High (ECRH)
  971
- Event Set Register (ESR)
  972
- Event Set Register (ESR) Field Descriptions
  972
- Event Set Register High (ESRH)
  973
- Event Set Register High (ESRH) Field Descriptions
  973
- Chained Event Register (CER)
  974
- Chained Event Register (CER) Field Descriptions
  974
- Chained Event Register High (CERH)
  974
- Chained Event Register High (CERH) Field Descriptions
  975
- Event Enable Register (EER)
  976
- Event Enable Register (EER) Field Descriptions
  976
- Event Enable Register High (EERH)
  976
- Event Enable Register High (EERH) Field Descriptions
  976
- Event Enable Clear Register (EECR)
  977
- Event Enable Clear Register (EECR) Field Descriptions
  977
- Event Enable Clear Register High (EECRH)
  977
- Event Enable Clear Register High (EECRH) Field Descriptions
  977
- Event Enable Set Register (EESR)
  978
- Event Enable Set Register (EESR) Field Descriptions
  978
- Event Enable Set Register High (EESRH)
  978
- Event Enable Set Register High (EESRH) Field Descriptions
  978
- Secondary Event Register (SER)
  979
- Secondary Event Register (SER) Field Descriptions
  979
- Secondary Event Register High (SERH)
  979
- Secondary Event Register High (SERH) Field Descriptions
  979
- Secondary Event Clear Register (SECR)
  980
- Secondary Event Clear Register (SECR) Field Descriptions
  980
- Secondary Event Clear Register High (SECRH)
  980
- Secondary Event Clear Register High (SECRH) Field Descriptions
  980
- Interrupt Enable Register (IER)
  981
- Interrupt Enable Register (IER) Field Descriptions
  981
- Interrupt Enable Register High (IERH)
  981
- Interrupt Enable Clear Register (IECR)
  982
- Interrupt Enable Clear Register (IECR) Field Descriptions
  982
- Interrupt Enable Clear Register High (IECRH)
  982
- Interrupt Enable Clear Register High (IECRH) Field Descriptions
  982
- Interrupt Enable Set Register (IESR)
  983
- Interrupt Enable Set Register (IESR) Field Descriptions
  983
- Interrupt Enable Set Register High (IESRH)
  983
- Interrupt Enable Set Register High (IESRH) Field Descriptions
  983
- Interrupt Pending Register (IPR)
  984
- Interrupt Pending Register (IPR) Field Descriptions
  984
- Interrupt Pending Register High (IPRH)
  984
- Interrupt Pending Register High (IPRH) Field Descriptions
  984
- Interrupt Clear Register (ICR)
  985
- Interrupt Clear Register (ICR) Field Descriptions
  985
- Interrupt Clear Register High (ICRH)
  985
- Interrupt Clear Register High (ICRH) Field Descriptions
  985
- Interrupt Evaluate Register (IEVAL)
  986
- Interrupt Evaluate Register (IEVAL) Field Descriptions
  986
- QDMA Event Register (QER)
  987
- QDMA Event Register (QER) Field Descriptions
  987
- QDMA Event Enable Register (QEER)
  988
- QDMA Event Enable Register (QEER) Field Descriptions
  988
- QDMA Event Enable Clear Register (QEECR)
  989
- QDMA Event Enable Clear Register (QEECR) Field Descriptions
  989
- QDMA Event Enable Set Register (QEESR)
  990
- QDMA Event Enable Set Register (QEESR) Field Descriptions
  990
- QDMA Secondary Event Register (QSER)
  991
- QDMA Secondary Event Register (QSER) Field Descriptions
  991
- QDMA Secondary Event Clear Register (QSECR)
  992
- QDMA Secondary Event Clear Register (QSECR) Field Descriptions
  992
- EDMA3TC Registers
  993
- Peripheral ID Register (PID)
  994
- Peripheral ID Register (PID) Field Descriptions
  994
- EDMA3TC Configuration Register (TCCFG)
  995
- EDMA3TC Configuration Register (TCCFG) Field Descriptions
  995
- EDMA3TC System Configuration (SYSCONFIG) Field Descriptions
  996
- EDMA3TC System Configuration Register (SYSCONFIG)
  996
- EDMA3TC Channel Status Register (TCSTAT)
  997
- EDMA3TC Channel Status Register (TCSTAT) Field Descriptions
  997
- Error Register (ERRSTAT)
  999
- Error Register (ERRSTAT) Field Descriptions
  999
- Error Enable Register (ERREN)
  1000
- Error Enable Register (ERREN) Field Descriptions
  1000
- Error Clear Register (ERRCLR)
  1001
- Error Clear Register (ERRCLR) Field Descriptions
  1001
- Error Details Register (ERRDET)
  1002
- Error Details Register (ERRDET) Field Descriptions
  1002
- Error Interrupt Command Register (ERRCMD)
  1003
- Error Interrupt Command Register (ERRCMD) Field Descriptions
  1003
- Read Rate Register (RDRATE)
  1004
- Read Rate Register (RDRATE) Field Descriptions
  1004
- Source Active Options Register (SAOPT)
  1005
- Source Active Options Register (SAOPT) Field Descriptions
  1005
- Source Active Count Register (SACNT)
  1007
- Source Active Count Register (SACNT) Field Descriptions
  1007
- Source Active Source Address Register (SASRC)
  1007
- Source Active Source Address Register (SASRC) Field Descriptions
  1007
- Source Active Destination Address Register (SADST)
  1008
- Source Active Destination Address Register (SADST) Field Descriptions
  1008
- Source Active Source B-Dimension Index Register (SABIDX)
  1008
- Source Active Source B-Dimension Index Register (SABIDX) Field Descriptions
  1008
- Source Active Memory Protection Proxy Register (SAMPPRXY)
  1009
- Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions
  1009
- Source Active Count Reload Register (SACNTRLD)
  1010
- Source Active Count Reload Register (SACNTRLD) Field Descriptions
  1010
- Source Active Source Address B-Reference Register (SASRCBREF)
  1010
- Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions
  1010
- Source Active Destination Address B-Reference Register (SADSTBREF)
  1011
- Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions
  1011
- Destination FIFO Options Register (Dfoptn)
  1012
- Destination FIFO Options Register (Dfoptn) Field Descriptions
  1012
- Destination FIFO Count Register (Dfcntn)
  1014
- Destination FIFO Count Register (Dfcntn) Field Descriptions
  1014
- Destination FIFO Source Address Register (Dfsrcn)
  1014
- Destination FIFO Source Address Register (Dfsrcn) Field Descriptions
  1014
- Destination FIFO B-Index Register (Dfbidxn)
  1015
- Destination FIFO B-Index Register (Dfbidxn) Field Descriptions
  1015
- Destination FIFO Destination Address Register (Dfdstn)
  1015
- Destination FIFO Destination Address Register (Dfdstn) Field Descriptions
  1015
- Destination FIFO Memory Protection Proxy Register (Dfmpprxyn)
  1016
- Destination FIFO Memory Protection Proxy Register (Dfmpprxyn) Field Descriptions
  1016
- Destination FIFO Count Reload Register (Dfcntrldn)
  1017
- Destination FIFO Count Reload Register (Dfcntrldn) Field Descriptions
  1017
- Destination FIFO Source Address B-Reference Register (Dfsrcbrefn)
  1017
- Destination FIFO Source Address B-Reference Register (Dfsrcbrefn) Field Descriptions
  1017
- Debug List
  1018
- Destination FIFO Destination Address B-Reference Register (Dfdstbrefn)
  1018
- Destination FIFO Destination Address B-Reference Register (Dfdstbrefn) Field Descriptions
  1018
- 12.2.1 TSC_ADC Connectivity Attributes
  1024
- TSC_ADC Integration
  1024
- TSC_ADC Clock Signals
  1025
- Functional Block Diagram
  1028
- Sequencer FSM
  1031
- Example Timing Diagram for Sequencer
  1032
- Tsc_Adc_Ss Registers
  1034
- REVISION Register
  1035
- REVISION Register Field Descriptions
  1035
- SYSCONFIG Register
  1036
- SYSCONFIG Register Field Descriptions
  1036
- IRQSTATUS_RAW Register
  1037
- IRQSTATUS_RAW Register Field Descriptions
  1038
- IRQSTATUS Register
  1039
- IRQSTATUS Register Field Descriptions
  1039
- IRQSTATUS Register Field Descriptions
  1040
- IRQENABLE_SET Register
  1041
- IRQENABLE_SET Register Field Descriptions
  1042
- IRQENABLE_CLR Register
  1043
- IRQENABLE_CLR Register Field Descriptions
  1044
- IRQWAKEUP Register
  1045
- IRQWAKEUP Register Field Descriptions
  1045
- DMAENABLE_SET Register
  1046
- DMAENABLE_CLR Register
  1047
- CTRL Register
  1048
- CTRL Register Field Descriptions
  1048
- ADCSTAT Register
  1049
- ADCSTAT Register Field Descriptions
  1049
- ADCRANGE Register
  1050
- ADCRANGE Register Field Descriptions
  1050
- ADC_CLKDIV Register
  1051
- ADC_CLKDIV Register Field Descriptions
  1051
- ADC_MISC Register
  1052
- ADC_MISC Register Field Descriptions
  1052
- STEPENABLE Register
  1053
- STEPENABLE Register Field Descriptions
  1053
- IDLECONFIG Register
  1054
- IDLECONFIG Register Field Descriptions
  1054
- TS_CHARGE_STEPCONFIG Register
  1055
- TS_CHARGE_STEPCONFIG Register Field Descriptions
  1055
- TS_CHARGE_DELAY Register
  1056
- TS_CHARGE_DELAY Register Field Descriptions
  1056
- STEPCONFIG1 Register
  1057
- STEPCONFIG1 Register Field Descriptions
  1057
- STEPDELAY1 Register
  1058
- STEPDELAY1 Register Field Descriptions
  1058
- STEPCONFIG2 Register
  1059
- STEPCONFIG2 Register Field Descriptions
  1059
- STEPDELAY2 Register
  1060
- STEPDELAY2 Register Field Descriptions
  1060
- STEPCONFIG3 Register
  1061
- STEPCONFIG3 Register Field Descriptions
  1061
- STEPDELAY3 Register
  1062
- STEPDELAY3 Register Field Descriptions
  1062
- STEPCONFIG4 Register
  1063
- STEPCONFIG4 Register Field Descriptions
  1063
- STEPDELAY4 Register
  1064
- STEPDELAY4 Register Field Descriptions
  1064
- STEPCONFIG5 Register
  1065
- STEPCONFIG5 Register Field Descriptions
  1065
- STEPDELAY5 Register
  1066
- STEPDELAY5 Register Field Descriptions
  1066
- STEPCONFIG6 Register
  1067
- STEPCONFIG6 Register Field Descriptions
  1067
- STEPDELAY6 Register
  1068
- STEPDELAY6 Register Field Descriptions
  1068
- STEPCONFIG7 Register
  1069
- STEPCONFIG7 Register Field Descriptions
  1069
- STEPDELAY7 Register
  1070
- STEPDELAY7 Register Field Descriptions
  1070
- STEPCONFIG8 Register
  1071
- STEPCONFIG8 Register Field Descriptions
  1071
- STEPDELAY8 Register
  1072
- STEPDELAY8 Register Field Descriptions
  1072
- STEPCONFIG9 Register
  1073
- STEPCONFIG9 Register Field Descriptions
  1073
- STEPDELAY9 Register
  1074
- STEPDELAY9 Register Field Descriptions
  1074
- STEPCONFIG10 Register
  1075
- STEPCONFIG10 Register Field Descriptions
  1075
- STEPDELAY10 Register
  1076
- STEPDELAY10 Register Field Descriptions
  1076
- STEPCONFIG11 Register
  1077
- STEPCONFIG11 Register Field Descriptions
  1077
- STEPDELAY11 Register
  1078
- STEPDELAY11 Register Field Descriptions
  1078
- STEPCONFIG12 Register
  1079
- STEPCONFIG12 Register Field Descriptions
  1079
- STEPDELAY12 Register
  1080
- STEPDELAY12 Register Field Descriptions
  1080
- STEPCONFIG13 Register
  1081
- STEPCONFIG13 Register Field Descriptions
  1081
- STEPDELAY13 Register
  1082
- STEPDELAY13 Register Field Descriptions
  1082
- STEPCONFIG14 Register
  1083
- STEPCONFIG14 Register Field Descriptions
  1083
- STEPDELAY14 Register
  1084
- STEPDELAY14 Register Field Descriptions
  1084
- STEPCONFIG15 Register
  1085
- STEPCONFIG15 Register Field Descriptions
  1085
- STEPDELAY15 Register
  1086
- STEPDELAY15 Register Field Descriptions
  1086
- STEPCONFIG16 Register
  1087
- STEPCONFIG16 Register Field Descriptions
  1087
- STEPDELAY16 Register
  1088
- STEPDELAY16 Register Field Descriptions
  1088
- FIFO0COUNT Register
  1089
- FIFO0COUNT Register Field Descriptions
  1089
- FIFO0THRESHOLD Register
  1090
- FIFO0THRESHOLD Register Field Descriptions
  1090
- DMA0REQ Register
  1091
- DMA0REQ Register Field Descriptions
  1091
- FIFO1COUNT Register
  1092
- FIFO1COUNT Register Field Descriptions
  1092
- FIFO1THRESHOLD Register
  1093
- FIFO1THRESHOLD Register Field Descriptions
  1093
- DMA1REQ Register
  1094
- DMA1REQ Register Field Descriptions
  1094
- FIFO0DATA Register
  1095
- FIFO0DATA Register Field Descriptions
  1095
- FIFO1DATA Register
  1096
- FIFO1DATA Register Field Descriptions
  1096
- LCD Controller
  1098
- 13.2.1 LCD Controller Connectivity Attributes
  1100
- LCD Controller Integration
  1100
- 13.2.3 LCD Controller Pin List
  1101
- LCD Controller Clock Signals
  1101
- Input and Output Clocks
  1102
- 13.3.2 LCD External I/O Signals
  1104
- Register Configuration for DMA Engine Programming
  1105
- LIDD I/O Name Map
  1107
- Operation Modes Supported by Raster Controller
  1108
- Logical Data Path for Raster Controller
  1109
- Bits-Per-Pixel Encoding for Palette Entry 0 Buffer
  1110
- Frame Buffer Structure
  1110
- Frame Buffer Size According to BPP
  1111
- Color/Grayscale Intensities and Modulation Rates
  1115
- Number of Colors/Shades of Gray Available on Screen
  1115
- Monochrome and Color Output
  1116
- Example of Subpicture
  1117
- Subpicture HOLS Bit
  1117
- Raster Mode Display Format
  1118
- Highlander 0.8 Interrupt Module Control Registers
  1119
- Palette Lookup Examples
  1126
- Lcd Registers
  1128
- PID Register
  1130
- PID Register Field Descriptions
  1130
- CTRL Register
  1131
- CTRL Register Field Descriptions
  1131
- LIDD_CTRL Register
  1132
- LIDD_CTRL Register Field Descriptions
  1132
- LIDD_CS0_CONF Register
  1133
- LIDD_CS0_CONF Register Field Descriptions
  1133
- LIDD_CS0_ADDR Register
  1134
- LIDD_CS0_ADDR Register Field Descriptions
  1134
- LIDD_CS0_DATA Register
  1135
- LIDD_CS0_DATA Register Field Descriptions
  1135
- LIDD_CS1_CONF Register
  1136
- LIDD_CS1_CONF Register Field Descriptions
  1136
- LIDD_CS1_ADDR Register
  1137
- LIDD_CS1_ADDR Register Field Descriptions
  1137
- LIDD_CS1_DATA Register
  1138
- LIDD_CS1_DATA Register Field Descriptions
  1138
- RASTER_CTRL Register
  1139
- RASTER_CTRL Register Field Descriptions
  1139
- RASTER_TIMING_0 Register
  1141
- RASTER_TIMING_0 Register Field Descriptions
  1141
- RASTER_TIMING_1 Register
  1142
- RASTER_TIMING_1 Register Field Descriptions
  1142
- RASTER_TIMING_2 Register
  1143
- RASTER_TIMING_2 Register Field Descriptions
  1143
- RASTER_SUBPANEL Register
  1145
- RASTER_SUBPANEL Register Field Descriptions
  1145
- RASTER_SUBPANEL2 Register
  1146
- RASTER_SUBPANEL2 Register Field Descriptions
  1146
- LCDDMA_CTRL Register
  1147
- LCDDMA_CTRL Register Field Descriptions
  1147
- LCDDMA_FB0_BASE Register
  1148
- LCDDMA_FB0_BASE Register Field Descriptions
  1148
- LCDDMA_FB0_CEILING Register
  1149
- LCDDMA_FB0_CEILING Register Field Descriptions
  1149
- LCDDMA_FB1_BASE Register
  1150
- LCDDMA_FB1_BASE Register Field Descriptions
  1150
- LCDDMA_FB1_CEILING Register
  1151
- LCDDMA_FB1_CEILING Register Field Descriptions
  1151
- SYSCONFIG Register
  1152
- SYSCONFIG Register Field Descriptions
  1152
- IRQSTATUS_RAW Register
  1153
- IRQSTATUS_RAW Register Field Descriptions
  1153
- IRQSTATUS_RAW Register Field Descriptions
  1154
- IRQSTATUS Register
  1155
- IRQSTATUS Register Field Descriptions
  1155
- IRQENABLE_SET Register
  1157
- IRQENABLE_SET Register Field Descriptions
  1157
- IRQENABLE_SET Register Field Descriptions
  1158
- IRQENABLE_CLEAR Register
  1159
- IRQENABLE_CLEAR Register Field Descriptions
  1159
- CLKC_ENABLE Register
  1161
- CLKC_ENABLE Register Field Descriptions
  1161
- CLKC_RESET Register
  1162
- CLKC_RESET Register Field Descriptions
  1162
- Unsupported CPGMAC Features
  1165
- Ethernet Switch Integration
  1166
- 14.2.1 Ethernet Switch Connectivity Attributes
  1167
- Ethernet Switch Clock Signals
  1168
- 14.2.3 Ethernet Switch Pin List
  1169
- Ethernet Switch RMII Clock Detail
  1170
- GMII Interface Signal Descriptions in GIG (1000Mbps) Mode
  1171
- MII Interface Connections
  1171
- GMII Interface Signal Descriptions in MII (100/10Mbps) Mode
  1172
- RMII Interface Connections
  1173
- RMII Interface Signal Descriptions
  1173
- RGMII Interface Connections
  1174
- RGMII Interface Signal Descriptions
  1175
- CPSW_3G Block Diagram
  1182
- Tx Buffer Descriptor Format
  1187
- Rx Buffer Descriptor Format
  1190
- VLAN Header Encapsulation Word
  1194
- VLAN Header Encapsulation Word Field Descriptions
  1194
- Free (Unused) Address Table Entry Bit Values
  1195
- Learned Address Control Bits
  1195
- Multicast Address Table Entry Bit Values
  1196
- Vlan/Multicast Address Table Entry Bit Values
  1196
- Unicast Address Table Entry Bit Values
  1197
- OUI Unicast Address Table Entry Bit Values
  1198
- Unicast Address Table Entry Bit Values
  1199
- VLAN Table Entry
  1200
- Operations of Emulation Control Input and Register Bits
  1210
- Rx Statistics Summary
  1219
- Tx Statistics Summary
  1220
- CPTS Block Diagram
  1228
- Event FIFO Misalignment Condition
  1230
- HW1/4_TSP_PUSH Connection
  1231
- Values of Messagetype Field
  1232
- MDIO Read Frame Format
  1233
- MDIO Write Frame Format
  1233
- Port TX State RAM Entry
  1236
- Port RX DMA State
  1237
- Cpsw_Ale Registers
  1240
- IDVER Register
  1241
- IDVER Register Field Descriptions
  1241
- CONTROL Register
  1242
- CONTROL Register Field Descriptions
  1242
- CONTROL Register Field Descriptions
  1243
- PRESCALE Register
  1244
- PRESCALE Register Field Descriptions
  1244
- UNKNOWN_VLAN Register
  1245
- UNKNOWN_VLAN Register Field Descriptions
  1245
- TBLCTL Register
  1246
- TBLCTL Register Field Descriptions
  1246
- TBLW2 Register
  1247
- TBLW2 Register Field Descriptions
  1247
- TBLW1 Register
  1248
- TBLW1 Register Field Descriptions
  1248
- TBLW0 Register
  1249
- TBLW0 Register Field Descriptions
  1249
- PORTCTL0 Register
  1250
- PORTCTL0 Register Field Descriptions
  1250
- PORTCTL1 Register
  1251
- PORTCTL1 Register Field Descriptions
  1251
- PORTCTL2 Register
  1252
- PORTCTL2 Register Field Descriptions
  1252
- PORTCTL3 Register
  1253
- PORTCTL3 Register Field Descriptions
  1253
- PORTCTL4 Register
  1254
- PORTCTL4 Register Field Descriptions
  1254
- PORTCTL5 Register
  1255
- PORTCTL5 Register Field Descriptions
  1255
- Cpsw_Cpdma Registers
  1256
- TX_IDVER Register
  1258
- TX_IDVER Register Field Descriptions
  1258
- TX_CONTROL Register
  1259
- TX_CONTROL Register Field Descriptions
  1259
- TX_TEARDOWN Register
  1260
- TX_TEARDOWN Register Field Descriptions
  1260
- RX_IDVER Register
  1261
- RX_IDVER Register Field Descriptions
  1261
- RX_CONTROL Register
  1262
- RX_CONTROL Register Field Descriptions
  1262
- RX_TEARDOWN Register
  1263
- RX_TEARDOWN Register Field Descriptions
  1263
- CPDMA_SOFT_RESET Register
  1264
- CPDMA_SOFT_RESET Register Field Descriptions
  1264
- DMACONTROL Register
  1265
- DMACONTROL Register Field Descriptions
  1265
- DMASTATUS Register
  1267
- DMASTATUS Register Field Descriptions
  1267
- RX_BUFFER_OFFSET Register
  1269
- RX_BUFFER_OFFSET Register Field Descriptions
  1269
- EMCONTROL Register
  1270
- EMCONTROL Register Field Descriptions
  1270
- TX_PRI0_RATE Register
  1271
- TX_PRI0_RATE Register Field Descriptions
  1271
- TX_PRI1_RATE Register
  1272
- TX_PRI1_RATE Register Field Descriptions
  1272
- TX_PRI2_RATE Register
  1273
- TX_PRI2_RATE Register Field Descriptions
  1273
- TX_PRI3_RATE Register
  1274
- TX_PRI3_RATE Register Field Descriptions
  1274
- TX_PRI4_RATE Register
  1275
- TX_PRI4_RATE Register Field Descriptions
  1275
- TX_PRI5_RATE Register
  1276
- TX_PRI5_RATE Register Field Descriptions
  1276
- TX_PRI6_RATE Register
  1277
- TX_PRI6_RATE Register Field Descriptions
  1277
- TX_PRI7_RATE Register
  1278
- TX_PRI7_RATE Register Field Descriptions
  1278
- TX_INTSTAT_RAW Register
  1279
- TX_INTSTAT_MASKED Register
  1280
- TX_INTSTAT_MASKED Register Field Descriptions
  1280
- TX_INTMASK_SET Register
  1281
- TX_INTMASK_CLEAR Register
  1282
- TX_INTMASK_CLEAR Register Field Descriptions
  1282
- CPDMA_IN_VECTOR Register
  1283
- CPDMA_IN_VECTOR Register Field Descriptions
  1283
- CPDMA_EOI_VECTOR Register
  1284
- CPDMA_EOI_VECTOR Register Field Descriptions
  1284
- RX_INTSTAT_RAW Register
  1285
- RX_INTSTAT_MASKED Register
  1286
- RX_INTSTAT_MASKED Register Field Descriptions
  1286
- RX_INTMASK_SET Register
  1287
- RX_INTMASK_CLEAR Register
  1288
- RX_INTMASK_CLEAR Register Field Descriptions
  1288
- DMA_INTSTAT_RAW Register
  1289
- DMA_INTSTAT_MASKED Register
  1290
- DMA_INTSTAT_MASKED Register Field Descriptions
  1290
- DMA_INTMASK_SET Register
  1291
- DMA_INTMASK_CLEAR Register
  1292
- DMA_INTMASK_CLEAR Register Field Descriptions
  1292
- RX0_PENDTHRESH Register
  1293
- RX0_PENDTHRESH Register Field Descriptions
  1293
- RX1_PENDTHRESH Register
  1294
- RX1_PENDTHRESH Register Field Descriptions
  1294
- RX2_PENDTHRESH Register
  1295
- RX2_PENDTHRESH Register Field Descriptions
  1295
- RX3_PENDTHRESH Register
  1296
- RX3_PENDTHRESH Register Field Descriptions
  1296
- RX4_PENDTHRESH Register
  1297
- RX4_PENDTHRESH Register Field Descriptions
  1297
- RX5_PENDTHRESH Register
  1298
- RX5_PENDTHRESH Register Field Descriptions
  1298
- RX6_PENDTHRESH Register
  1299
- RX6_PENDTHRESH Register Field Descriptions
  1299
- RX7_PENDTHRESH Register
  1300
- RX7_PENDTHRESH Register Field Descriptions
  1300
- RX0_FREEBUFFER Register
  1301
- RX0_FREEBUFFER Register Field Descriptions
  1301
- RX1_FREEBUFFER Register
  1302
- RX1_FREEBUFFER Register Field Descriptions
  1302
- RX2_FREEBUFFER Register
  1303
- RX2_FREEBUFFER Register Field Descriptions
  1303
- RX3_FREEBUFFER Register
  1304
- RX3_FREEBUFFER Register Field Descriptions
  1304
- RX4_FREEBUFFER Register
  1305
- RX4_FREEBUFFER Register Field Descriptions
  1305
- RX5_FREEBUFFER Register
  1306
- RX5_FREEBUFFER Register Field Descriptions
  1306
- RX6_FREEBUFFER Register
  1307
- RX6_FREEBUFFER Register Field Descriptions
  1307
- Cpsw_Cpts Registers
  1308
- RX7_FREEBUFFER Register
  1308
- RX7_FREEBUFFER Register Field Descriptions
  1308
- CPTS_IDVER Register
  1310
- CPTS_IDVER Register Field Descriptions
  1310
- CPTS_CONTROL Register
  1311
- CPTS_CONTROL Register Field Descriptions
  1311
- CPTS_TS_PUSH Register
  1312
- CPTS_TS_PUSH Register Field Descriptions
  1312
- CPTS_TS_LOAD_VAL Register
  1313
- CPTS_TS_LOAD_EN Register
  1314
- CPTS_INTSTAT_RAW Register
  1315
- CPTS_INTSTAT_MASKED Register
  1316
- CPTS_INTSTAT_MASKED Register Field Descriptions
  1316
- CPTS_INT_ENABLE Register
  1317
- CPTS_INT_ENABLE Register Field Descriptions
  1317
- CPTS_EVENT_POP Register
  1318
- CPTS_EVENT_LOW Register
  1319
- CPTS_EVENT_HIGH Register
  1320
- CPTS_EVENT_HIGH Register Field Descriptions
  1320
- Cpdma_Stateram Registers
  1321
- Cpsw_Stats Registers
  1321
- TX0_HDP Register
  1324
- TX1_HDP Register
  1325
- TX2_HDP Register
  1326
- TX3_HDP Register
  1327
- TX4_HDP Register
  1328
- TX5_HDP Register
  1329
- TX6_HDP Register
  1330
- TX7_HDP Register
  1331
- RX0_HDP Register
  1332
- RX1_HDP Register
  1333
- RX2_HDP Register
  1334
- RX3_HDP Register
  1335
- RX4_HDP Register
  1336
- RX5_HDP Register
  1337
- RX6_HDP Register
  1338
- RX7_HDP Register
  1339
- TX0_CP Register
  1340
- TX1_CP Register
  1341
- TX2_CP Register
  1342
- TX3_CP Register
  1343
- TX4_CP Register
  1344
- TX5_CP Register
  1345
- TX6_CP Register
  1346
- TX7_CP Register
  1347
- RX0_CP Register
  1348
- RX1_CP Register
  1349
- RX2_CP Register
  1350
- RX3_CP Register
  1351
- RX4_CP Register
  1352
- RX5_CP Register
  1353
- RX6_CP Register
  1354
- Cpsw_Port Registers
  1355
- RX7_CP Register
  1355
- P0_CONTROL Register
  1357
- P0_CONTROL Register Field Descriptions
  1357
- P0_MAX_BLKS Register
  1358
- P0_MAX_BLKS Register Field Descriptions
  1358
- P0_BLK_CNT Register
  1359
- P0_TX_IN_CTL Register
  1360
- P0_PORT_VLAN Register
  1361
- P0_PORT_VLAN Register Field Descriptions
  1361
- P0_TX_PRI_MAP Register
  1362
- P0_CPDMA_TX_PRI_MAP Register
  1363
- P0_CPDMA_RX_CH_MAP Register
  1364
- P0_RX_DSCP_PRI_MAP0 Register
  1365
- P0_RX_DSCP_PRI_MAP0 Register Field Descriptions
  1365
- P0_RX_DSCP_PRI_MAP1 Register
  1366
- P0_RX_DSCP_PRI_MAP1 Register Field Descriptions
  1366
- P0_RX_DSCP_PRI_MAP2 Register
  1367
- P0_RX_DSCP_PRI_MAP2 Register Field Descriptions
  1367
- P0_RX_DSCP_PRI_MAP3 Register
  1368
- P0_RX_DSCP_PRI_MAP3 Register Field Descriptions
  1368
- P0_RX_DSCP_PRI_MAP4 Register
  1369
- P0_RX_DSCP_PRI_MAP4 Register Field Descriptions
  1369
- P0_RX_DSCP_PRI_MAP5 Register
  1370
- P0_RX_DSCP_PRI_MAP5 Register Field Descriptions
  1370
- P0_RX_DSCP_PRI_MAP6 Register
  1371
- P0_RX_DSCP_PRI_MAP6 Register Field Descriptions
  1371
- P0_RX_DSCP_PRI_MAP7 Register
  1372
- P0_RX_DSCP_PRI_MAP7 Register Field Descriptions
  1372
- P1_CONTROL Register
  1373
- P1_CONTROL Register Field Descriptions
  1373
- P1_MAX_BLKS Register
  1375
- P1_MAX_BLKS Register Field Descriptions
  1375
- P1_BLK_CNT Register
  1376
- P1_TX_IN_CTL Register
  1377
- P1_PORT_VLAN Register
  1378
- P1_PORT_VLAN Register Field Descriptions
  1378
- P1_TX_PRI_MAP Register
  1379
- P1_TS_SEQ_MTYPE Register
  1380
- P1_TS_SEQ_MTYPE Register Field Descriptions
  1380
- P1_SA_LO Register
  1381
- P1_SA_HI Register
  1382
- P1_SEND_PERCENT Register
  1383
- P1_SEND_PERCENT Register Field Descriptions
  1383
- P1_RX_DSCP_PRI_MAP0 Register
  1384
- P1_RX_DSCP_PRI_MAP0 Register Field Descriptions
  1384
- P1_RX_DSCP_PRI_MAP1 Register
  1385
- P1_RX_DSCP_PRI_MAP1 Register Field Descriptions
  1385
- P1_RX_DSCP_PRI_MAP2 Register
  1386
- P1_RX_DSCP_PRI_MAP2 Register Field Descriptions
  1386
- P1_RX_DSCP_PRI_MAP3 Register
  1387
- P1_RX_DSCP_PRI_MAP3 Register Field Descriptions
  1387
- P1_RX_DSCP_PRI_MAP4 Register
  1388
- P1_RX_DSCP_PRI_MAP4 Register Field Descriptions
  1388
- P1_RX_DSCP_PRI_MAP5 Register
  1389
- P1_RX_DSCP_PRI_MAP5 Register Field Descriptions
  1389
- P1_RX_DSCP_PRI_MAP6 Register
  1390
- P1_RX_DSCP_PRI_MAP6 Register Field Descriptions
  1390
- P1_RX_DSCP_PRI_MAP7 Register
  1391
- P1_RX_DSCP_PRI_MAP7 Register Field Descriptions
  1391
- P2_CONTROL Register
  1392
- P2_CONTROL Register Field Descriptions
  1392
- P2_MAX_BLKS Register
  1394
- P2_MAX_BLKS Register Field Descriptions
  1394
- P2_BLK_CNT Register
  1395
- P2_TX_IN_CTL Register
  1396
- P2_PORT_VLAN Register
  1397
- P2_PORT_VLAN Register Field Descriptions
  1397
- P2_TX_PRI_MAP Register
  1398
- P2_TS_SEQ_MTYPE Register
  1399
- P2_TS_SEQ_MTYPE Register Field Descriptions
  1399
- P2_SA_LO Register
  1400
- P2_SA_HI Register
  1401
- P2_SEND_PERCENT Register
  1402
- P2_SEND_PERCENT Register Field Descriptions
  1402
- P2_RX_DSCP_PRI_MAP0 Register
  1403
- P2_RX_DSCP_PRI_MAP0 Register Field Descriptions
  1403
- P2_RX_DSCP_PRI_MAP1 Register
  1404
- P2_RX_DSCP_PRI_MAP1 Register Field Descriptions
  1404
- P2_RX_DSCP_PRI_MAP2 Register
  1405
- P2_RX_DSCP_PRI_MAP2 Register Field Descriptions
  1405
- P2_RX_DSCP_PRI_MAP3 Register
  1406
- P2_RX_DSCP_PRI_MAP3 Register Field Descriptions
  1406
- P2_RX_DSCP_PRI_MAP4 Register
  1407
- P2_RX_DSCP_PRI_MAP4 Register Field Descriptions
  1407
- P2_RX_DSCP_PRI_MAP5 Register
  1408
- P2_RX_DSCP_PRI_MAP5 Register Field Descriptions
  1408
- P2_RX_DSCP_PRI_MAP6 Register
  1409
- P2_RX_DSCP_PRI_MAP6 Register Field Descriptions
  1409
- P2_RX_DSCP_PRI_MAP7 Register
  1410
- P2_RX_DSCP_PRI_MAP7 Register Field Descriptions
  1410
- IDVER Register
  1412
- IDVER Register Field Descriptions
  1412
- MACCONTROL Register
  1413
- MACCONTROL Register Field Descriptions
  1413
- MACSTATUS Register
  1416
- MACSTATUS Register Field Descriptions
  1416
- SOFT_RESET Register
  1417
- SOFT_RESET Register Field Descriptions
  1417
- RX_MAXLEN Register
  1418
- RX_MAXLEN Register Field Descriptions
  1418
- BOFFTEST Register
  1419
- BOFFTEST Register Field Descriptions
  1419
- RX_PAUSE Register
  1420
- RX_PAUSE Register Field Descriptions
  1420
- TX_PAUSE Register
  1421
- TX_PAUSE Register Field Descriptions
  1421
- EMCONTROL Register
  1422
- EMCONTROL Register Field Descriptions
  1422
- RX_PRI_MAP Register
  1423
- TX_GAP Register
  1424
- ID_VER Register
  1425
- CONTROL Register
  1426
- CONTROL Register Field Descriptions
  1426
- SOFT_RESET Register
  1427
- SOFT_RESET Register Field Descriptions
  1427
- STAT_PORT_EN Register
  1428
- PTYPE Register
  1429
- PTYPE Register Field Descriptions
  1429
- SOFT_IDLE Register
  1430
- SOFT_IDLE Register Field Descriptions
  1430
- THRU_RATE Register
  1431
- THRU_RATE Register Field Descriptions
  1431
- GAP_THRESH Register
  1432
- GAP_THRESH Register Field Descriptions
  1432
- TX_START_WDS Register
  1433
- FLOW_CONTROL Register
  1434
- FLOW_CONTROL Register Field Descriptions
  1434
- VLAN_LTYPE Register
  1435
- VLAN_LTYPE Register Field Descriptions
  1435
- TS_LTYPE Register
  1436
- TS_LTYPE Register Field Descriptions
  1436
- DLR_LTYPE Register
  1437
- DLR_LTYPE Register Field Descriptions
  1437
- Cpsw_Wr Registers
  1438
- IDVER Register
  1439
- IDVER Register Field Descriptions
  1439
- SOFT_RESET Register
  1440
- SOFT_RESET Register Field Descriptions
  1440
- CONTROL Register
  1441
- INT_CONTROL Register
  1442
- INT_CONTROL Register Field Descriptions
  1442
- C0_RX_THRESH_EN Register
  1443
- C0_RX_EN Register
  1444
- C0_TX_EN Register
  1445
- C0_MISC_EN Register
  1446
- C1_RX_THRESH_EN Register
  1447
- C1_RX_EN Register
  1448
- C1_TX_EN Register
  1449
- C1_MISC_EN Register
  1450
- C2_RX_THRESH_EN Register
  1451
- C2_RX_EN Register
  1452
- C2_TX_EN Register
  1453
- C2_MISC_EN Register
  1454
- C0_RX_THRESH_STAT Register
  1455
- C0_RX_THRESH_STAT Register Field Descriptions
  1455
- C0_RX_STAT Register
  1456
- C0_RX_STAT Register Field Descriptions
  1456
- C0_TX_STAT Register
  1457
- C0_TX_STAT Register Field Descriptions
  1457
- C0_MISC_STAT Register
  1458
- C0_MISC_STAT Register Field Descriptions
  1458
- C1_RX_THRESH_STAT Register
  1459
- C1_RX_THRESH_STAT Register Field Descriptions
  1459
- C1_RX_STAT Register
  1460
- C1_RX_STAT Register Field Descriptions
  1460
- C1_TX_STAT Register
  1461
- C1_TX_STAT Register Field Descriptions
  1461
- C1_MISC_STAT Register
  1462
- C1_MISC_STAT Register Field Descriptions
  1462
- C2_RX_THRESH_STAT Register
  1463
- C2_RX_THRESH_STAT Register Field Descriptions
  1463
- C2_RX_STAT Register
  1464
- C2_RX_STAT Register Field Descriptions
  1464
- C2_TX_STAT Register
  1465
- C2_TX_STAT Register Field Descriptions
  1465
- C2_MISC_STAT Register
  1466
- C2_MISC_STAT Register Field Descriptions
  1466
- C0_RX_IMAX Register
  1467
- C0_RX_IMAX Register Field Descriptions
  1467
- C0_TX_IMAX Register
  1468
- C0_TX_IMAX Register Field Descriptions
  1468
- C1_RX_IMAX Register
  1469
- C1_RX_IMAX Register Field Descriptions
  1469
- C1_TX_IMAX Register
  1470
- C1_TX_IMAX Register Field Descriptions
  1470
- C2_RX_IMAX Register
  1471
- C2_RX_IMAX Register Field Descriptions
  1471
- C2_TX_IMAX Register
  1472
- C2_TX_IMAX Register Field Descriptions
  1472
- RGMII_CTL Register
  1473
- Management Data Input/Output (MDIO) Registers
  1474
- MDIO Version Register (MDIOVER)
  1474
- MDIO Version Register (MDIOVER) Field Descriptions
  1474
- MDIO Control Register (MDIOCONTROL)
  1475
- MDIO Control Register (MDIOCONTROL) Field Descriptions
  1475
- PHY Acknowledge Status Register (MDIOALIVE)
  1476
- PHY Acknowledge Status Register (MDIOALIVE) Field Descriptions
  1476
- PHY Link Status Register (MDIOLINK)
  1476
- PHY Link Status Register (MDIOLINK) Field Descriptions
  1476
- MDIO Link Status Change Interrupt Register (Masked Value) (MDIOLINKINTMASKED)
  1477
- MDIO Link Status Change Interrupt Register (Masked Value) (MDIOLINKINTMASKED) Field Descriptions
  1477
- MDIO Link Status Change Interrupt Register (MDIOLINKINTRAW)
  1477
- MDIO Link Status Change Interrupt Register (MDIOLINKINTRAW) Field Descriptions
  1477
- MDIO User Command Complete Interrupt Register (Masked Value) (MDIOUSERINTMASKED)
  1478
- MDIO User Command Complete Interrupt Register (Masked Value) (MDIOUSERINTMASKED) Field Descriptions
  1478
- MDIO User Command Complete Interrupt Register (Raw Value) (MDIOUSERINTRAW)
  1478
- MDIO User Command Complete Interrupt Mask Set Register (MDIOUSERINTMASKSET)
  1479
- MDIO User Command Complete Interrupt Mask Set Register (MDIOUSERINTMASKSET) Field Descriptions
  1479
- MDIO User Command Complete Interrupt Mask Clear Register (MDIOUSERINTMASKCLR)
  1480
- MDIO User Command Complete Interrupt Mask Clear Register (MDIOUSERINTMASKCLR) Field Descriptions
  1480
- MDIO User Access Register 0 (MDIOUSERACCESS0)
  1481
- MDIO User Access Register 0 (MDIOUSERACCESS0) Field Descriptions
  1481
- MDIO User PHY Select Register 0 (MDIOUSERPHYSEL0)
  1482
- MDIO User PHY Select Register 0 (MDIOUSERPHYSEL0) Field Descriptions
  1482
- MDIO User Access Register 1 (MDIOUSERACCESS1)
  1483
- MDIO User Access Register 1 (MDIOUSERACCESS1) Field Descriptions
  1483
- MDIO User PHY Select Register 1 (MDIOUSERPHYSEL1)
  1484
- MDIO User PHY Select Register 1 (MDIOUSERPHYSEL1) Field Descriptions
  1484
- Unsupported Features
  1487
- PWMSS Connectivity Attributes
  1488
- PWMSS Integration
  1488
- PWMSS Clock Signals
  1489
- PWMSS Pin List
  1489
- Pwmss Registers
  1489
- IDVER Register
  1490
- IDVER Register Field Descriptions
  1490
- SYSCONFIG Register
  1491
- SYSCONFIG Register Field Descriptions
  1491
- CLKCONFIG Register
  1492
- CLKCONFIG Register Field Descriptions
  1492
- CLKSTATUS Register
  1493
- CLKSTATUS Register Field Descriptions
  1493
- Multiple Epwm Modules
  1495
- Submodules and Signal Connections for an Epwm Module
  1496
- Epwm Submodules and Critical Internal Signal Interconnects
  1497
- Submodule Configuration Parameters
  1498
- Time-Base Submodule Block Diagram
  1501
- Time-Base Submodule Registers
  1503
- Time-Base Submodule Signals and Registers
  1503
- Key Time-Base Signals
  1504
- Time-Base Frequency and Period
  1505
- Time-Base Counter Synchronization Scheme
  1506
- Time-Base Up-Count Mode Waveforms
  1508
- Time-Base Down-Count Mode Waveforms
  1509
- Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count down on Synchronization Event
  1509
- Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count up on Synchronization Event
  1510
- Counter-Compare Submodule
  1511
- Counter-Compare Submodule Signals and Registers
  1511
- Counter-Compare Submodule Key Signals
  1512
- Counter-Compare Submodule Registers
  1512
- Counter-Compare Event Waveforms in Up-Count Mode
  1514
- Counter-Compare Events in Down-Count Mode
  1514
- Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count down on Synchronization Event
  1515
- Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count up on Synchronization Event
  1515
- Action-Qualifier Submodule
  1516
- Action-Qualifier Submodule Registers
  1516
- Action-Qualifier Submodule Inputs and Outputs
  1517
- Action-Qualifier Submodule Possible Input Events
  1517
- Possible Action-Qualifier Actions for Epwmxa and Epwmxb Outputs
  1518
- Action-Qualifier Event Priority for Down-Count Mode
  1519
- Action-Qualifier Event Priority for Up-Count Mode
  1519
- Action-Qualifier Event Priority for Up-Down-Count Mode
  1519
- Behavior if CMPA/CMPB Is Greater than the Period
  1520
- Up-Down-Count Mode Symmetrical Waveform
  1521
- Up, Single Edge Asymmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb-Active High
  1522
- Epwmx Initialization for
  1523
- Epwmx Run Time Changes for
  1523
- Up, Single Edge Asymmetric Waveform with Independent Modulation on Epwmxa and Epwmxb-Active Low
  1524
- Epwmx Initialization for
  1525
- Epwmx Run Time Changes for
  1525
- Up-Count, Pulse Placement Asymmetric Waveform with Independent Modulation on Epwmxa
  1526
- Epwmx Initialization for
  1527
- Epwmx Run Time Changes for
  1527
- Up-Down-Count, Dual Edge Symmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb - Active Low
  1528
- Epwmx Initialization for
  1529
- Epwmx Run Time Changes for
  1529
- Up-Down-Count, Dual Edge Symmetric Waveform, with Independent Modulation on Epwmxa and Epwmxb - Complementary
  1530
- Epwmx Initialization for
  1531
- Epwmx Run Time Changes for
  1531
- Up-Down-Count, Dual Edge Asymmetric Waveform, with Independent Modulation on Epwmxa-Active Low
  1532
- Epwmx Initialization for
  1533
- Epwmx Run Time Changes for
  1533
- Dead-Band Generator Submodule
  1534
- Dead-Band Generator Submodule Registers
  1534
- Configuration Options for the Dead-Band Generator Submodule
  1535
- Classical Dead-Band Operating Modes
  1536
- Dead-Band Waveforms for Typical Cases (0% < Duty < 100%)
  1537
- PWM-Chopper Submodule
  1538
- PWM-Chopper Submodule Registers
  1538
- PWM-Chopper Submodule Signals and Registers
  1539
- PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses
  1540
- Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only
  1540
- PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses
  1541
- Trip-Zone Submodule
  1542
- Trip-Zone Submodule Registers
  1543
- Possible Actions on a Trip Event
  1544
- Trip-Zone Submodule Interrupt Logic
  1545
- Trip-Zone Submodule Mode Control Logic
  1545
- Event-Trigger Submodule
  1546
- Event-Trigger Submodule Registers
  1546
- Event-Trigger Submodule Inter-Connectivity to Interrupt Controller
  1547
- Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs
  1547
- Event-Trigger Interrupt Generator
  1549
- HRPWM System Interface
  1550
- Resolution Calculations for Conventionally Generated PWM
  1551
- Resolution for PWM and HRPWM
  1551
- HRPWM Submodule Registers
  1552
- Operating Logic Using MEP
  1552
- Relationship between MEP Steps, PWM Frequency and Resolution
  1553
- CMPA Vs Duty (Left), and [CMPA:CMPAHR] Vs Duty (Right)
  1554
- Required PWM Waveform for a Requested Duty
  1554
- High % Duty Cycle Range Limitation Example When PWM Frequency = 1 Mhz
  1556
- Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 Mhz
  1556
- Simplified Epwm Module
  1557
- EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
  1558
- Control of Four Buck Stages. here F
  1559
- Pwm1
  1559
- Pwm1 Pwm2 Pwm3 Pwm4
  1559
- Buck Waveforms for
  1560
- EPWM1 Initialization for
  1561
- EPWM2 Initialization for
  1561
- EPWM3 Initialization for
  1561
- Control of Four Buck Stages
  1562
- Pwm1 )
  1562
- Pwm2 Pwm1)
  1563
- EPWM1 Initialization for
  1564
- EPWM2 Initialization for
  1564
- Pwm2 Pwm1
  1566
- EPWM1 Initialization for
  1567
- EPWM2 Initialization for
  1567
- Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control
  1568
- EPWM1 Initialization for
  1570
- EPWM2 Initialization for
  1570
- EPWM3 Initialization for
  1571
- Configuring Two PWM Modules for Phase Control
  1572
- Timing Waveforms Associated with Phase Control between 2 Modules
  1573
- Control of a 3-Phase Interleaved DC/DC Converter
  1574
- EPWM1 Initialization for
  1576
- EPWM2 Initialization for
  1576
- EPWM3 Initialization for
  1577
- Pwm2 Pwm1)
  1578
- ZVS Full-H Bridge Waveforms
  1579
- EPWM1 Initialization for
  1580
- EPWM2 Initialization for
  1580
- Epwm Module Control and Status Registers Grouped by Submodule
  1581
- Time-Base Control Register (TBCTL)
  1582
- Time-Base Control Register (TBCTL) Field Descriptions
  1582
- Time-Base Submodule Registers
  1582
- Time-Base Phase Register (TBPHS)
  1584
- Time-Base Status Register (TBSTS)
  1584
- Time-Base Status Register (TBSTS) Field Descriptions
  1584
- Time-Base Counter Register (TBCNT)
  1585
- Time-Base Counter Register (TBCNT) Field Descriptions
  1585
- Time-Base Phase Register (TBPHS) Field Descriptions
  1585
- Counter-Compare Submodule Registers
  1586
- Time-Base Period Register (TBPRD)
  1586
- Time-Base Period Register (TBPRD) Field Descriptions
  1586
- Counter-Compare Control Register (CMPCTL)
  1587
- Counter-Compare Control Register (CMPCTL) Field Descriptions
  1587
- Counter-Compare a Register (CMPA)
  1588
- Counter-Compare a Register (CMPA) Field Descriptions
  1588
- Action-Qualifier Submodule Registers
  1589
- Counter-Compare B Register (CMPB)
  1589
- Counter-Compare B Register (CMPB) Field Descriptions
  1589
- Action-Qualifier Output a Control Register (AQCTLA)
  1590
- Action-Qualifier Output B Control Register (AQCTLB)
  1591
- Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions
  1591
- Action-Qualifier Software Force Register (AQSFRC)
  1592
- Action-Qualifier Software Force Register (AQSFRC) Field Descriptions
  1592
- Action-Qualifier Continuous Software Force Register (AQCSFRC)
  1593
- Action-Qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions
  1593
- Dead-Band Generator Submodule Registers
  1593
- Dead-Band Generator Control Register (DBCTL)
  1594
- Dead-Band Generator Control Register (DBCTL) Field Descriptions
  1594
- Dead-Band Generator Falling Edge Delay Register (DBFED)
  1595
- Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions
  1595
- Dead-Band Generator Rising Edge Delay Register (DBRED)
  1595
- Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions
  1595
- Trip-Zone Select Register (TZSEL)
  1596
- Trip-Zone Submodule Registers
  1596
- Trip-Zone Submodule Select Register (TZSEL) Field Descriptions
  1596
- Trip-Zone Control Register (TZCTL)
  1597
- Trip-Zone Control Register (TZCTL) Field Descriptions
  1597
- Trip-Zone Enable Interrupt Register (TZEINT)
  1597
- Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions
  1597
- Trip-Zone Flag Register (TZFLG)
  1598
- Trip-Zone Flag Register (TZFLG) Field Descriptions
  1598
- Trip-Zone Clear Register (TZCLR)
  1599
- Trip-Zone Clear Register (TZCLR) Field Descriptions
  1599
- Trip-Zone Force Register (TZFRC)
  1599
- Trip-Zone Force Register (TZFRC) Field Descriptions
  1599
- Event-Trigger Selection Register (ETSEL)
  1600
- Event-Trigger Selection Register (ETSEL) Field Descriptions
  1600
- Event-Trigger Submodule Registers
  1600
- Event-Trigger Prescale Register (ETPS)
  1601
- Event-Trigger Prescale Register (ETPS) Field Descriptions
  1601
- Event-Trigger Clear Register (ETCLR)
  1602
- Event-Trigger Clear Register (ETCLR) Field Descriptions
  1602
- Event-Trigger Flag Register (ETFLG)
  1602
- Event-Trigger Flag Register (ETFLG) Field Descriptions
  1602
- Event-Trigger Force Register (ETFRC)
  1603
- Event-Trigger Force Register (ETFRC) Field Descriptions
  1603
- High-Resolution PWM Submodule Registers
  1604
- PWM-Chopper Control Register (PCCTL)
  1604
- PWM-Chopper Control Register (PCCTL) Bit Descriptions
  1604
- Counter-Compare a High-Resolution Register (CMPAHR)
  1605
- Counter-Compare a High-Resolution Register (CMPAHR) Field Descriptions
  1605
- Time-Base Phase High-Resolution Register (TBPHSHR)
  1605
- Time-Base Phase High-Resolution Register (TBPHSHR) Field Descriptions
  1605
- HRPWM Control Register (HRCTL)
  1606
- HRPWM Control Register (HRCTL) Field Descriptions
  1606
- Multiple Ecap Modules
  1608
- Capture and APWM Modes of Operation
  1609
- Capture Function Diagram
  1610
- Event Prescale Control
  1611
- Prescale Function Waveforms
  1611
- Continuous/One-Shot Block Diagram
  1612
- Counter and Synchronization Block Diagram
  1613
- Interrupts in Ecap Module
  1615
- PWM Waveform Details of APWM Mode Operation
  1616
- Capture Sequence for Absolute Time-Stamp, Rising Edge Detect
  1619
- ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger
  1620
- Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect
  1621
- ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger
  1622
- Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect
  1623
- ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger
  1624
- Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect
  1625
- ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers
  1626
- PWM Waveform Details of APWM Mode Operation
  1627
- ECAP Initialization for APWM Mode
  1628
- Multichannel PWM Example Using 4 Ecap Modules
  1629
- ECAP1 Initialization for Multichannel PWM Generation with Synchronization
  1630
- ECAP2 Initialization for Multichannel PWM Generation with Synchronization
  1630
- ECAP3 Initialization for Multichannel PWM Generation with Synchronization
  1630
- ECAP4 Initialization for Multichannel PWM Generation with Synchronization
  1630
- Multiphase (Channel) Interleaved PWM Example Using 3 Ecap Modules
  1632
- ECAP1 Initialization for Multichannel PWM Generation with Phase Control
  1633
- ECAP2 Initialization for Multichannel PWM Generation with Phase Control
  1633
- ECAP3 Initialization for Multichannel PWM Generation with Phase Control
  1633
- Ecap Registers
  1634
- TSCTR Register
  1635
- TSCTR Register Field Descriptions
  1635
- CTRPHS Register
  1636
- CTRPHS Register Field Descriptions
  1636
- CAP1 Register
  1637
- CAP1 Register Field Descriptions
  1637
- CAP2 Register
  1638
- CAP2 Register Field Descriptions
  1638
- CAP3 Register
  1639
- CAP3 Register Field Descriptions
  1639
- CAP4 Register
  1640
- CAP4 Register Field Descriptions
  1640
- ECCTL1 Register
  1641
- ECCTL1 Register Field Descriptions
  1641
- ECCTL2 Register
  1643
- ECCTL2 Register Field Descriptions
  1643
- ECEINT Register
  1645
- ECEINT Register Field Descriptions
  1645
- ECFLG Register
  1646
- ECFLG Register Field Descriptions
  1646
- ECCLR Register
  1647
- ECCLR Register Field Descriptions
  1647
- ECFRC Register
  1648
- ECFRC Register Field Descriptions
  1648
- REVID Register
  1649
- REVID Register Field Descriptions
  1649
- Optical Encoder Disk
  1650
- Index Pulse Example
  1651
- QEP Encoder Output Signal for Forward/Reverse Movement
  1651
- Functional Block Diagram of the Eqep Peripheral
  1654
- Functional Block Diagram of Decoder Unit
  1655
- Quadrature Decoder Truth Table
  1656
- Quadrature Decoder State Machine
  1657
- Quadrature-Clock and Direction Decoding
  1657
- Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh)
  1659
- Position Counter Underflow/Overflow (QPOSMAX = 4)
  1660
- Software Index Marker for 1000-Line Encoder (QEPCTL[IEL] = 1)
  1662
- Strobe Event Latch (QEPCTL[SEL] = 1)
  1663
- Eqep Position-Compare Unit
  1664
- Eqep Position-Compare Event Generation Points
  1665
- Eqep Position-Compare Sync Output Pulse Stretcher
  1665
- Eqep Edge Capture Unit
  1667
- Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)
  1667
- Eqep Edge Capture Unit - Timing Details
  1668
- Eqep Watchdog Timer
  1669
- EQEP Interrupt Generation
  1670
- Eqep Unit Time Base
  1670
- Eqep Registers
  1672
- Eqep Maximum Position Count Register (QPOSMAX)
  1673
- Eqep Maximum Position Count Register (QPOSMAX) Field Descriptions
  1673
- Eqep Position Counter Initialization Register (QPOSINIT)
  1673
- Eqep Position Counter Initialization Register (QPOSINIT) Field Descriptions
  1673
- Eqep Position Counter Register (QPOSCNT)
  1673
- Eqep Position Counter Register (QPOSCNT) Field Descriptions
  1673
- Eqep Index Position Latch Register (QPOSILAT)
  1674
- Eqep Index Position Latch Register (QPOSILAT) Field Descriptions
  1674
- Eqep Position-Compare Register (QPOSCMP)
  1674
- Eqep Position-Compare Register (QPOSCMP) Field Descriptions
  1674
- Eqep Strobe Position Latch Register (QPOSSLAT)
  1674
- Eqep Strobe Position Latch Register (QPOSSLAT) Field Descriptions
  1674
- Eqep Position Counter Latch Register (QPOSLAT)
  1675
- Eqep Position Counter Latch Register (QPOSLAT) Field Descriptions
  1675
- Eqep Unit Period Register (QUPRD)
  1675
- Eqep Unit Period Register (QUPRD) Field Descriptions
  1675
- Eqep Unit Timer Register (QUTMR)
  1675
- Eqep Unit Timer Register (QUTMR) Field Descriptions
  1675
- Eqep Watchdog Period Register (QWDPRD)
  1676
- Eqep Watchdog Period Register (QWDPRD) Field Description
  1676
- Eqep Watchdog Timer Register (QWDTMR)
  1676
- Eqep Watchdog Timer Register (QWDTMR) Field Descriptions
  1676
- Eqep Decoder Control Register (QDECCTL) Field Descriptions
  1677
- QEP Decoder Control Register (QDECCTL)
  1677
- Eqep Control Register (QEPCTL)
  1678
- Eqep Control Register (QEPCTL) Field Descriptions
  1678
- Eqep Capture Control Register (QCAPCTL)
  1680
- Eqep Capture Control Register (QCAPCTL) Field Descriptions
  1680
- Eqep Position-Compare Control Register (QPOSCTL)
  1681
- Eqep Position-Compare Control Register (QPOSCTL) Field Descriptions
  1681
- Eqep Interrupt Enable Register (QEINT)
  1682
- Eqep Interrupt Enable Register (QEINT) Field Descriptions
  1682
- Eqep Interrupt Flag Register (QFLG)
  1683
- Eqep Interrupt Flag Register (QFLG) Field Descriptions
  1683
- Eqep Interrupt Clear Register (QCLR)
  1684
- Eqep Interrupt Clear Register (QCLR) Field Descriptions
  1684
- Eqep Interrupt Force Register (QFRC)
  1686
- Eqep Interrupt Force Register (QFRC) Field Descriptions
  1686
- Eqep Status Register (QEPSTS)
  1687
- Eqep Status Register (QEPSTS) Field Descriptions
  1687
- Eqep Capture Period Register (QCPRD)
  1688
- Eqep Capture Period Register (QCPRD) Field Descriptions
  1688
- Eqep Capture Time Register (QCTMR) Field Descriptions
  1688
- Eqep Capture Timer Latch Register (QCTMRLAT)
  1688
- Eqep Capture Timer Latch Register (QCTMRLAT) Field Descriptions
  1688
- Eqep Capture Timer Register (QCTMR)
  1688
- Eqep Capture Period Latch Register (QCPRDLAT)
  1689
- Eqep Capture Period Latch Register (QCPRDLAT) Field Descriptions
  1689
- Eqep Revision ID Register (REVID)
  1689
- Eqep Revision ID Register (REVID) Field Descriptions
  1689
- USB Connectivity Attributes
  1694
- USB Integration
  1694
- USB Clock Signals
  1695
- USB Pin List
  1695
- USB GPIO Integration
  1696
- CPU Actions at Transfer Phases
  1704
- Sequence of Transfer
  1705
- Flow Chart of Setup Stage of a Control Transfer in Peripheral Mode
  1707
- Flow Chart of Transmit Data Stage of a Control Transfer in Peripheral Mode
  1708
- Flow Chart of Receive Data Stage of a Control Transfer in Peripheral Mode
  1709
- PERI_TXCSR Register Bit Configuration for Bulk in Transactions
  1711
- PERI_RXCSR Register Bit Configuration for Bulk out Transactions
  1713
- PERI_RXCSR Register Bit Configuration for Isochronous out Transactions
  1716
- Isochronous out Error Handling: Peripheral Mode
  1717
- Flow Chart of Setup Stage of a Control Transfer in Host Mode
  1720
- Flow Chart of Data Stage (in Data Phase) of a Control Transfer in Host Mode
  1721
- Flow Chart of Data Stage (out Data Phase) of a Control Transfer in Host Mode
  1723
- Flow Chart of Status Stage of Zero Data Request or Write Request of a Control Transfer in Host Mode
  1724
- Chart of Status Stage of a Read Request of a Control Transfer in Host Mode
  1726
- Packet Descriptor Layout
  1736
- Packet Descriptor Word 0 (PD0) Bit Field Descriptions
  1736
- Packet Descriptor Word 1 (PD1) Bit Field Descriptions
  1737
- Packet Descriptor Word 2 (PD2) Bit Field Descriptions
  1737
- Packet Descriptor Word 3 (PD3) Bit Field Descriptions
  1737
- Packet Descriptor Word 4 (PD4) Bit Field Descriptions
  1738
- Packet Descriptor Word 5 (PD5) Bit Field Descriptions
  1738
- Packet Descriptor Word 6 (PD6) Bit Field Descriptions
  1738
- Packet Descriptor Word 7 (PD7) Bit Field Descriptions
  1738
- Buffer Descriptor (BD) Layout
  1739
- Buffer Descriptor Word 0 (BD0) Bit Field Descriptions
  1739
- Buffer Descriptor Word 1 (BD1) Bit Field Descriptions
  1739
- Buffer Descriptor Word 2 (BD2) Bit Field Descriptions
  1739
- Buffer Descriptor Word 3 (BD3) Bit Field Descriptions
  1739
- Buffer Descriptor Word 4 (BD4) Bit Field Descriptions
  1740
- Buffer Descriptor Word 5 (BD5) Bit Field Descriptions
  1740
- Buffer Descriptor Word 6 (BD6) Bit Field Descriptions
  1740
- Buffer Descriptor Word 7 (BD7) Bit Field Descriptions
  1740
- Teardown Descriptor Layout
  1741
- Teardown Descriptor Word 0 Bit Field Descriptions
  1741
- Teardown Descriptor Words 1 to 7 Bit Field Descriptions
  1741
- Queue-Endpoint Assignments
  1742
- Relationship between Memory Regions and Linking RAM
  1746
- High-Level Transmit and Receive Data Transfer Example
  1751
- Transmit Descriptors and Queue Status Configuration
  1753
- Transmit USB Data Flow Example (Initialization)
  1754
- Receive Buffer Descriptors and Queue Status Configuration
  1756
- Receive USB Data Flow Example (Initialization)
  1757
- Bytes Test Packet Content
  1758
- Usbss Registers
  1760
- REVREG Register
  1762
- REVREG Register Field Descriptions
  1762
- SYSCONFIG Register
  1763
- SYSCONFIG Register Field Descriptions
  1763
- IRQSTATRAW Register
  1764
- IRQSTATRAW Register Field Descriptions
  1764
- IRQSTAT Register
  1765
- IRQSTAT Register Field Descriptions
  1765
- IRQENABLER Register
  1766
- IRQENABLER Register Field Descriptions
  1766
- IRQCLEARR Register
  1767
- IRQCLEARR Register Field Descriptions
  1767
- IRQDMATHOLDTX00 Register
  1768
- IRQDMATHOLDTX00 Register Field Descriptions
  1768
- IRQDMATHOLDTX01 Register
  1769
- IRQDMATHOLDTX01 Register Field Descriptions
  1769
- IRQDMATHOLDTX02 Register
  1770
- IRQDMATHOLDTX02 Register Field Descriptions
  1770
- IRQDMATHOLDTX03 Register
  1771
- IRQDMATHOLDTX03 Register Field Descriptions
  1771
- IRQDMATHOLDRX00 Register
  1772
- IRQDMATHOLDRX00 Register Field Descriptions
  1772
- IRQDMATHOLDRX01 Register
  1773
- IRQDMATHOLDRX01 Register Field Descriptions
  1773
- IRQDMATHOLDRX02 Register
  1774
- IRQDMATHOLDRX02 Register Field Descriptions
  1774
- IRQDMATHOLDRX03 Register
  1775
- IRQDMATHOLDRX03 Register Field Descriptions
  1775
- IRQDMATHOLDTX10 Register
  1776
- IRQDMATHOLDTX10 Register Field Descriptions
  1776
- IRQDMATHOLDTX11 Register
  1777
- IRQDMATHOLDTX11 Register Field Descriptions
  1777
- IRQDMATHOLDTX12 Register
  1778
- IRQDMATHOLDTX12 Register Field Descriptions
  1778
- IRQDMATHOLDTX13 Register
  1779
- IRQDMATHOLDTX13 Register Field Descriptions
  1779
- IRQDMATHOLDRX10 Register
  1780
- IRQDMATHOLDRX10 Register Field Descriptions
  1780
- IRQDMATHOLDRX11 Register
  1781
- IRQDMATHOLDRX11 Register Field Descriptions
  1781
- IRQDMATHOLDRX12 Register
  1782
- IRQDMATHOLDRX12 Register Field Descriptions
  1782
- IRQDMATHOLDRX13 Register
  1783
- IRQDMATHOLDRX13 Register Field Descriptions
  1783
- IRQDMAENABLE0 Register
  1784
- IRQDMAENABLE0 Register Field Descriptions
  1784
- IRQDMAENABLE1 Register
  1785
- IRQDMAENABLE1 Register Field Descriptions
  1785
- IRQFRAMETHOLDTX00 Register
  1786
- IRQFRAMETHOLDTX00 Register Field Descriptions
  1786
- IRQFRAMETHOLDTX01 Register
  1787
- IRQFRAMETHOLDTX01 Register Field Descriptions
  1787
- IRQFRAMETHOLDTX02 Register
  1788
- IRQFRAMETHOLDTX02 Register Field Descriptions
  1788
- IRQFRAMETHOLDTX03 Register
  1789
- IRQFRAMETHOLDTX03 Register Field Descriptions
  1789
- IRQFRAMETHOLDRX00 Register
  1790
- IRQFRAMETHOLDRX00 Register Field Descriptions
  1790
- IRQFRAMETHOLDRX01 Register
  1791
- IRQFRAMETHOLDRX01 Register Field Descriptions
  1791
- IRQFRAMETHOLDRX02 Register
  1792
- IRQFRAMETHOLDRX02 Register Field Descriptions
  1792
- IRQFRAMETHOLDRX03 Register
  1793
- IRQFRAMETHOLDRX03 Register Field Descriptions
  1793
- IRQFRAMETHOLDTX10 Register
  1794
- IRQFRAMETHOLDTX10 Register Field Descriptions
  1794
- IRQFRAMETHOLDTX11 Register
  1795
- IRQFRAMETHOLDTX11 Register Field Descriptions
  1795
- IRQFRAMETHOLDTX12 Register
  1796
- IRQFRAMETHOLDTX12 Register Field Descriptions
  1796
- IRQFRAMETHOLDTX13 Register
  1797
- IRQFRAMETHOLDTX13 Register Field Descriptions
  1797
- IRQFRAMETHOLDRX10 Register
  1798
- IRQFRAMETHOLDRX10 Register Field Descriptions
  1798
- IRQFRAMETHOLDRX11 Register
  1799
- IRQFRAMETHOLDRX11 Register Field Descriptions
  1799
- IRQFRAMETHOLDRX12 Register
  1800
- IRQFRAMETHOLDRX12 Register Field Descriptions
  1800
- IRQFRAMETHOLDRX13 Register
  1801
- IRQFRAMETHOLDRX13 Register Field Descriptions
  1801
- IRQFRAMEENABLE0 Register
  1802
- IRQFRAMEENABLE0 Register Field Descriptions
  1802
- IRQFRAMEENABLE1 Register
  1803
- IRQFRAMEENABLE1 Register Field Descriptions
  1803
- Usb0_Ctrl Registers
  1803
- USB0REV Register
  1805
- USB0REV Register Field Descriptions
  1805
- USB0CTRL Register
  1806
- USB0CTRL Register Field Descriptions
  1806
- USB0STAT Register
  1808
- USB0STAT Register Field Descriptions
  1808
- USB0IRQMSTAT Register
  1809
- USB0IRQMSTAT Register Field Descriptions
  1809
- USB0IRQSTATRAW0 Register
  1810
- USB0IRQSTATRAW0 Register Field Descriptions
  1810
- USB0IRQSTATRAW1 Register
  1812
- USB0IRQSTATRAW1 Register Field Descriptions
  1812
- USB0IRQSTAT0 Register
  1814
- USB0IRQSTAT0 Register Field Descriptions
  1814
- USB0IRQSTAT1 Register
  1816
- USB0IRQSTAT1 Register Field Descriptions
  1816
- USB0IRQENABLESET0 Register
  1818
- USB0IRQENABLESET0 Register Field Descriptions
  1818
- USB0IRQENABLESET1 Register
  1820
- USB0IRQENABLESET1 Register Field Descriptions
  1820
- USB0IRQENABLECLR0 Register
  1822
- USB0IRQENABLECLR0 Register Field Descriptions
  1822
- USB0IRQENABLECLR1 Register
  1824
- USB0IRQENABLECLR1 Register Field Descriptions
  1824
- USB0TXMODE Register
  1826
- USB0TXMODE Register Field Descriptions
  1826
- USB0RXMODE Register
  1828
- USB0RXMODE Register Field Descriptions
  1828
- USB0GENRNDISEP1 Register
  1832
- USB0GENRNDISEP1 Register Field Descriptions
  1832
- USB0GENRNDISEP2 Register
  1833
- USB0GENRNDISEP2 Register Field Descriptions
  1833
- USB0GENRNDISEP3 Register
  1834
- USB0GENRNDISEP3 Register Field Descriptions
  1834
- USB0GENRNDISEP4 Register
  1835
- USB0GENRNDISEP4 Register Field Descriptions
  1835
- USB0GENRNDISEP5 Register
  1836
- USB0GENRNDISEP5 Register Field Descriptions
  1836
- USB0GENRNDISEP6 Register
  1837
- USB0GENRNDISEP6 Register Field Descriptions
  1837
- USB0GENRNDISEP7 Register
  1838
- USB0GENRNDISEP7 Register Field Descriptions
  1838
- USB0GENRNDISEP8 Register
  1839
- USB0GENRNDISEP8 Register Field Descriptions
  1839
- USB0GENRNDISEP9 Register
  1840
- USB0GENRNDISEP9 Register Field Descriptions
  1840
- USB0GENRNDISEP10 Register
  1841
- USB0GENRNDISEP10 Register Field Descriptions
  1841
- USB0GENRNDISEP11 Register
  1842
- USB0GENRNDISEP11 Register Field Descriptions
  1842
- USB0GENRNDISEP12 Register
  1843
- USB0GENRNDISEP12 Register Field Descriptions
  1843
- USB0GENRNDISEP13 Register
  1844
- USB0GENRNDISEP13 Register Field Descriptions
  1844
- USB0GENRNDISEP14 Register
  1845
- USB0GENRNDISEP14 Register Field Descriptions
  1845
- USB0GENRNDISEP15 Register
  1846
- USB0GENRNDISEP15 Register Field Descriptions
  1846
- USB0AUTOREQ Register
  1847
- USB0AUTOREQ Register Field Descriptions
  1847
- USB0SRPFIXTIME Register
  1849
- USB0SRPFIXTIME Register Field Descriptions
  1849
- USB0_TDOWN Register
  1850
- USB0_TDOWN Register Field Descriptions
  1850
- USB0UTMI Register
  1851
- USB0UTMI Register Field Descriptions
  1851
- USB0MGCUTMILB Register
  1852
- USB0MGCUTMILB Register Field Descriptions
  1852
- USB0MODE Register
  1853
- USB0MODE Register Field Descriptions
  1853
- Usb1_Ctrl Registers
  1853
- USB1REV Register
  1855
- USB1REV Register Field Descriptions
  1855
- USB1CTRL Register
  1856
- USB1CTRL Register Field Descriptions
  1856
- USB1STAT Register
  1858
- USB1STAT Register Field Descriptions
  1858
- USB1IRQMSTAT Register
  1859
- USB1IRQMSTAT Register Field Descriptions
  1859
- USB1IRQSTATRAW0 Register
  1860
- USB1IRQSTATRAW0 Register Field Descriptions
  1860
- USB1IRQSTATRAW1 Register
  1862
- USB1IRQSTATRAW1 Register Field Descriptions
  1862
- USB1IRQSTAT0 Register
  1864
- USB1IRQSTAT0 Register Field Descriptions
  1864
- USB1IRQSTAT1 Register
  1866
- USB1IRQSTAT1 Register Field Descriptions
  1866
- USB1IRQENABLESET0 Register
  1868
- USB1IRQENABLESET0 Register Field Descriptions
  1868
- USB1IRQENABLESET1 Register
  1870
- USB1IRQENABLESET1 Register Field Descriptions
  1870
- USB1IRQENABLECLR0 Register
  1872
- USB1IRQENABLECLR0 Register Field Descriptions
  1872
- USB1IRQENABLECLR1 Register
  1874
- USB1IRQENABLECLR1 Register Field Descriptions
  1874
- USB1TXMODE Register
  1876
- USB1TXMODE Register Field Descriptions
  1876
- USB1RXMODE Register
  1878
- USB1RXMODE Register Field Descriptions
  1878
- USB1GENRNDISEP1 Register
  1880
- USB1GENRNDISEP1 Register Field Descriptions
  1880
- USB1GENRNDISEP2 Register
  1881
- USB1GENRNDISEP2 Register Field Descriptions
  1881
- USB1GENRNDISEP3 Register
  1882
- USB1GENRNDISEP3 Register Field Descriptions
  1882
- USB1GENRNDISEP4 Register
  1883
- USB1GENRNDISEP4 Register Field Descriptions
  1883
- USB1GENRNDISEP5 Register
  1884
- USB1GENRNDISEP5 Register Field Descriptions
  1884
- USB1GENRNDISEP6 Register
  1885
- USB1GENRNDISEP6 Register Field Descriptions
  1885
- USB1GENRNDISEP7 Register
  1886
- USB1GENRNDISEP7 Register Field Descriptions
  1886
- USB1GENRNDISEP8 Register
  1887
- USB1GENRNDISEP8 Register Field Descriptions
  1887
- USB1GENRNDISEP9 Register
  1888
- USB1GENRNDISEP9 Register Field Descriptions
  1888
- USB1GENRNDISEP10 Register
  1889
- USB1GENRNDISEP10 Register Field Descriptions
  1889
- USB1GENRNDISEP11 Register
  1890
- USB1GENRNDISEP11 Register Field Descriptions
  1890
- USB1GENRNDISEP12 Register
  1891
- USB1GENRNDISEP12 Register Field Descriptions
  1891
- USB1GENRNDISEP13 Register
  1892
- USB1GENRNDISEP13 Register Field Descriptions
  1892
- USB1GENRNDISEP14 Register
  1893
- USB1GENRNDISEP14 Register Field Descriptions
  1893
- USB1GENRNDISEP15 Register
  1894
- USB1GENRNDISEP15 Register Field Descriptions
  1894
- USB1AUTOREQ Register
  1895
- USB1AUTOREQ Register Field Descriptions
  1895
- USB1SRPFIXTIME Register
  1897
- USB1SRPFIXTIME Register Field Descriptions
  1897
- USB1TDOWN Register
  1898
- USB1TDOWN Register Field Descriptions
  1898
- USB1UTMI Register
  1899
- USB1UTMI Register Field Descriptions
  1899
- USB1UTMILB Register
  1900
- USB1UTMILB Register Field Descriptions
  1900
- USB1MODE Register
  1901
- USB1MODE Register Field Descriptions
  1901
- Usb2Phy Registers
  1901
- Termination_Control Register
  1903
- Termination_Control Register Field Descriptions
  1903
- RX_CALIB Register
  1904
- RX_CALIB Register Field Descriptions
  1904
- DLLHS_2 Register
  1906
- RX_TEST_2 Register
  1907
- CHRG_DET Register
  1908
- CHRG_DET Register Field Descriptions
  1909
- PWR_CNTL Register
  1910
- PWR_CNTL Register Field Descriptions
  1910
- UTMI_INTERFACE_CNTL_1 Register
  1911
- UTMI_INTERFACE_CNTL_2 Register
  1912
- UTMI_INTERFACE_CNTL_2 Register Field Descriptions
  1913
- BIST Register
  1914
- BIST Register Field Descriptions
  1914
- BIST_CRC Register
  1915
- CDR_BIST2 Register
  1916
- CDR_BIST2 Register Field Descriptions
  1916
- GPIO Register
  1917
- GPIO Register Field Descriptions
  1917
- DLLHS Register
  1918
- DLLHS Register Field Descriptions
  1918
- USB2PHYCM_CONFIG Register
  1919
- USB2PHYCM_CONFIG Register Field Descriptions
  1919
- AD_INTERFACE_REG1 Register
  1920
- AD_INTERFACE_REG1 Register Field Descriptions
  1920
- AD_INTERFACE_REG2 Register
  1922
- AD_INTERFACE_REG2 Register Field Descriptions
  1922
- AD_INTERFACE_REG3 Register
  1924
- AD_INTERFACE_REG3 Register Field Descriptions
  1924
- ANA_CONFIG2 Register
  1925
- ANA_CONFIG2 Register Field Descriptions
  1925
- Cppi_Dma Registers
  1925
- DMAREVID Register
  1929
- DMAREVID Register Field Descriptions
  1929
- TDFDQ Register
  1930
- TDFDQ Register Field Descriptions
  1930
- DMAEMU Register
  1931
- DMAEMU Register Field Descriptions
  1931
- TXGCR0 Register
  1932
- TXGCR0 Register Field Descriptions
  1932
- RXGCR0 Register
  1933
- RXGCR0 Register Field Descriptions
  1933
- RXHPCRA0 Register
  1935
- RXHPCRA0 Register Field Descriptions
  1935
- RXHPCRB0 Register
  1936
- RXHPCRB0 Register Field Descriptions
  1936
- TXGCR1 Register
  1937
- TXGCR1 Register Field Descriptions
  1937
- RXGCR1 Register
  1938
- RXGCR1 Register Field Descriptions
  1938
- RXHPCRA1 Register
  1940
- RXHPCRA1 Register Field Descriptions
  1940
- RXHPCRB1 Register
  1941
- RXHPCRB1 Register Field Descriptions
  1941
- TXGCR2 Register
  1942
- TXGCR2 Register Field Descriptions
  1942
- RXGCR2 Register
  1943
- RXGCR2 Register Field Descriptions
  1943
- RXHPCRA2 Register
  1945
- RXHPCRA2 Register Field Descriptions
  1945
- RXHPCRB2 Register
  1946
- RXHPCRB2 Register Field Descriptions
  1946
- TXGCR3 Register
  1947
- TXGCR3 Register Field Descriptions
  1947
- RXGCR3 Register
  1948
- RXGCR3 Register Field Descriptions
  1948
- RXHPCRA3 Register
  1950
- RXHPCRA3 Register Field Descriptions
  1950
- RXHPCRB3 Register
  1951
- RXHPCRB3 Register Field Descriptions
  1951
- TXGCR4 Register
  1952
- TXGCR4 Register Field Descriptions
  1952
- RXGCR4 Register
  1953
- RXGCR4 Register Field Descriptions
  1953
- RXHPCRA4 Register
  1955
- RXHPCRA4 Register Field Descriptions
  1955
- RXHPCRB4 Register
  1956
- RXHPCRB4 Register Field Descriptions
  1956
- TXGCR5 Register
  1957
- TXGCR5 Register Field Descriptions
  1957
- RXGCR5 Register
  1958
- RXGCR5 Register Field Descriptions
  1958
- RXHPCRA5 Register
  1960
- RXHPCRA5 Register Field Descriptions
  1960
- RXHPCRB5 Register
  1961
- RXHPCRB5 Register Field Descriptions
  1961
- TXGCR6 Register
  1962
- TXGCR6 Register Field Descriptions
  1962
- RXGCR6 Register
  1963
- RXGCR6 Register Field Descriptions
  1963
- RXHPCRA6 Register
  1965
- RXHPCRA6 Register Field Descriptions
  1965
- RXHPCRB6 Register
  1966
- RXHPCRB6 Register Field Descriptions
  1966
- TXGCR7 Register
  1967
- TXGCR7 Register Field Descriptions
  1967
- RXGCR7 Register
  1968
- RXGCR7 Register Field Descriptions
  1968
- RXHPCRA7 Register
  1970
- RXHPCRA7 Register Field Descriptions
  1970
- RXHPCRB7 Register
  1971
- RXHPCRB7 Register Field Descriptions
  1971
- TXGCR8 Register
  1972
- TXGCR8 Register Field Descriptions
  1972
- RXGCR8 Register
  1973
- RXGCR8 Register Field Descriptions
  1973
- RXHPCRA8 Register
  1975
- RXHPCRA8 Register Field Descriptions
  1975
- RXHPCRB8 Register
  1976
- RXHPCRB8 Register Field Descriptions
  1976
- TXGCR9 Register
  1977
- TXGCR9 Register Field Descriptions
  1977
- RXGCR9 Register
  1978
- RXGCR9 Register Field Descriptions
  1978
- RXHPCRA9 Register
  1980
- RXHPCRA9 Register Field Descriptions
  1980
- RXHPCRB9 Register
  1981
- RXHPCRB9 Register Field Descriptions
  1981
- TXGCR10 Register
  1982
- TXGCR10 Register Field Descriptions
  1982
- RXGCR10 Register
  1983
- RXGCR10 Register Field Descriptions
  1983
- RXHPCRA10 Register
  1985
- RXHPCRA10 Register Field Descriptions
  1985
- RXHPCRB10 Register
  1986
- RXHPCRB10 Register Field Descriptions
  1986
- TXGCR11 Register
  1987
- TXGCR11 Register Field Descriptions
  1987
- RXGCR11 Register
  1988
- RXGCR11 Register Field Descriptions
  1988
- RXHPCRA11 Register
  1990
- RXHPCRA11 Register Field Descriptions
  1990
- RXHPCRB11 Register
  1991
- RXHPCRB11 Register Field Descriptions
  1991
- TXGCR12 Register
  1992
- TXGCR12 Register Field Descriptions
  1992
- RXGCR12 Register
  1993
- RXGCR12 Register Field Descriptions
  1993
- RXHPCRA12 Register
  1995
- RXHPCRA12 Register Field Descriptions
  1995
- RXHPCRB12 Register
  1996
- RXHPCRB12 Register Field Descriptions
  1996
- TXGCR13 Register
  1997
- TXGCR13 Register Field Descriptions
  1997
- RXGCR13 Register
  1998
- RXGCR13 Register Field Descriptions
  1998
- RXHPCRA13 Register
  2000
- RXHPCRA13 Register Field Descriptions
  2000
- RXHPCRB13 Register
  2001
- RXHPCRB13 Register Field Descriptions
  2001
- TXGCR14 Register
  2002
- TXGCR14 Register Field Descriptions
  2002
- RXGCR14 Register
  2003
- RXGCR14 Register Field Descriptions
  2003
- RXHPCRA14 Register
  2005
- RXHPCRA14 Register Field Descriptions
  2005
- RXHPCRB14 Register
  2006
- RXHPCRB14 Register Field Descriptions
  2006
- TXGCR15 Register
  2007
- TXGCR15 Register Field Descriptions
  2007
- RXGCR15 Register
  2008
- RXGCR15 Register Field Descriptions
  2008
- RXHPCRA15 Register
  2010
- RXHPCRA15 Register Field Descriptions
  2010
- RXHPCRB15 Register
  2011
- RXHPCRB15 Register Field Descriptions
  2011
- TXGCR16 Register
  2012
- TXGCR16 Register Field Descriptions
  2012
- RXGCR16 Register
  2013
- RXGCR16 Register Field Descriptions
  2013
- RXHPCRA16 Register
  2015
- RXHPCRA16 Register Field Descriptions
  2015
- RXHPCRB16 Register
  2016
- RXHPCRB16 Register Field Descriptions
  2016
- TXGCR17 Register
  2017
- TXGCR17 Register Field Descriptions
  2017
- RXGCR17 Register
  2018
- RXGCR17 Register Field Descriptions
  2018
- RXHPCRA17 Register
  2020
- RXHPCRA17 Register Field Descriptions
  2020
- RXHPCRB17 Register
  2021
- RXHPCRB17 Register Field Descriptions
  2021
- TXGCR18 Register
  2022
- TXGCR18 Register Field Descriptions
  2022
- RXGCR18 Register
  2023
- RXGCR18 Register Field Descriptions
  2023
- RXHPCRA18 Register
  2025
- RXHPCRA18 Register Field Descriptions
  2025
- RXHPCRB18 Register
  2026
- RXHPCRB18 Register Field Descriptions
  2026
- TXGCR19 Register
  2027
- TXGCR19 Register Field Descriptions
  2027
- RXGCR19 Register
  2028
- RXGCR19 Register Field Descriptions
  2028
- RXHPCRA19 Register
  2030
- RXHPCRA19 Register Field Descriptions
  2030
- RXHPCRB19 Register
  2031
- RXHPCRB19 Register Field Descriptions
  2031
- TXGCR20 Register
  2032
- TXGCR20 Register Field Descriptions
  2032
- RXGCR20 Register
  2033
- RXGCR20 Register Field Descriptions
  2033
- RXHPCRA20 Register
  2035
- RXHPCRA20 Register Field Descriptions
  2035
- RXHPCRB20 Register
  2036
- RXHPCRB20 Register Field Descriptions
  2036
- TXGCR21 Register
  2037
- TXGCR21 Register Field Descriptions
  2037
- RXGCR21 Register
  2038
- RXGCR21 Register Field Descriptions
  2038
- RXHPCRA21 Register
  2040
- RXHPCRA21 Register Field Descriptions
  2040
- RXHPCRB21 Register
  2041
- RXHPCRB21 Register Field Descriptions
  2041
- TXGCR22 Register
  2042
- TXGCR22 Register Field Descriptions
  2042
- RXGCR22 Register
  2043
- RXGCR22 Register Field Descriptions
  2043
- RXHPCRA22 Register
  2045
- RXHPCRA22 Register Field Descriptions
  2045
- RXHPCRB22 Register
  2046
- RXHPCRB22 Register Field Descriptions
  2046
- TXGCR23 Register
  2047
- TXGCR23 Register Field Descriptions
  2047
- RXGCR23 Register
  2048
- RXGCR23 Register Field Descriptions
  2048
- RXHPCRA23 Register
  2050
- RXHPCRA23 Register Field Descriptions
  2050
- RXHPCRB23 Register
  2051
- RXHPCRB23 Register Field Descriptions
  2051
- TXGCR24 Register
  2052
- TXGCR24 Register Field Descriptions
  2052
- RXGCR24 Register
  2053
- RXGCR24 Register Field Descriptions
  2053
- RXHPCRA24 Register
  2055
- RXHPCRA24 Register Field Descriptions
  2055
- RXHPCRB24 Register
  2056
- RXHPCRB24 Register Field Descriptions
  2056
- TXGCR25 Register
  2057
- TXGCR25 Register Field Descriptions
  2057
- RXGCR25 Register
  2058
- RXGCR25 Register Field Descriptions
  2058
- RXHPCRA25 Register
  2060
- RXHPCRA25 Register Field Descriptions
  2060
- RXHPCRB25 Register
  2061
- RXHPCRB25 Register Field Descriptions
  2061
- TXGCR26 Register
  2062
- TXGCR26 Register Field Descriptions
  2062
- RXGCR26 Register
  2063
- RXGCR26 Register Field Descriptions
  2063
- RXHPCRA26 Register
  2065
- RXHPCRA26 Register Field Descriptions
  2065
- RXHPCRB26 Register
  2066
- RXHPCRB26 Register Field Descriptions
  2066
- TXGCR27 Register
  2067
- TXGCR27 Register Field Descriptions
  2067
- RXGCR27 Register
  2068
- RXGCR27 Register Field Descriptions
  2068
- RXHPCRA27 Register
  2070
- RXHPCRA27 Register Field Descriptions
  2070
- RXHPCRB27 Register
  2071
- RXHPCRB27 Register Field Descriptions
  2071
- TXGCR28 Register
  2072
- TXGCR28 Register Field Descriptions
  2072
- RXGCR28 Register
  2073
- RXGCR28 Register Field Descriptions
  2073
- RXHPCRA28 Register
  2075
- RXHPCRA28 Register Field Descriptions
  2075
- RXHPCRB28 Register
  2076
- RXHPCRB28 Register Field Descriptions
  2076
- TXGCR29 Register
  2077
- TXGCR29 Register Field Descriptions
  2077
- RXGCR29 Register
  2078
- RXGCR29 Register Field Descriptions
  2078
- RXHPCRA29 Register
  2080
- RXHPCRA29 Register Field Descriptions
  2080
- Cppi_Dma_Scheduler Registers
  2081
- RXHPCRB29 Register
  2081
- RXHPCRB29 Register Field Descriptions
  2081
- DMA_SCHED_CTRL Register
  2082
- DMA_SCHED_CTRL Register Field Descriptions
  2082
- WORD0 to WORD63 Register
  2083
- WORD0 to WORD63 Register Field Descriptions
  2083
- Queue_Mgr Registers
  2084
- QMGRREVID Register
  2109
- QMGRREVID Register Field Descriptions
  2109
- QMGRRST Register
  2110
- QMGRRST Register Field Descriptions
  2110
- FDBSC0 Register
  2111
- FDBSC0 Register Field Descriptions
  2111
- FDBSC1 Register
  2112
- FDBSC1 Register Field Descriptions
  2112
- FDBSC2 Register
  2113
- FDBSC2 Register Field Descriptions
  2113
- FDBSC3 Register
  2114
- FDBSC3 Register Field Descriptions
  2114
- FDBSC4 Register
  2115
- FDBSC4 Register Field Descriptions
  2115
- FDBSC5 Register
  2116
- FDBSC5 Register Field Descriptions
  2116
- FDBSC6 Register
  2117
- FDBSC6 Register Field Descriptions
  2117
- FDBSC7 Register
  2118
- FDBSC7 Register Field Descriptions
  2118
- LRAM0BASE Register
  2119
- LRAM0BASE Register Field Descriptions
  2119
- LRAM0SIZE Register
  2120
- LRAM0SIZE Register Field Descriptions
  2120
- LRAM1BASE Register
  2121
- LRAM1BASE Register Field Descriptions
  2121
- PEND0 Register
  2122
- PEND0 Register Field Descriptions
  2122
- PEND1 Register
  2123
- PEND1 Register Field Descriptions
  2123
- PEND2 Register
  2124
- PEND2 Register Field Descriptions
  2124
- PEND3 Register
  2125
- PEND3 Register Field Descriptions
  2125
- PEND4 Register
  2126
- PEND4 Register Field Descriptions
  2126
- QMEMRBASE0 Register
  2127
- QMEMRBASE0 Register Field Descriptions
  2127
- QMEMCTRL0 Register
  2128
- QMEMCTRL0 Register Field Descriptions
  2128
- QMEMRBASE1 Register
  2129
- QMEMRBASE1 Register Field Descriptions
  2129
- QMEMCTRL1 Register
  2130
- QMEMCTRL1 Register Field Descriptions
  2130
- QMEMRBASE2 Register
  2131
- QMEMRBASE2 Register Field Descriptions
  2131
- QMEMCTRL2 Register
  2132
- QMEMCTRL2 Register Field Descriptions
  2132
- QMEMRBASE3 Register
  2133
- QMEMRBASE3 Register Field Descriptions
  2133
- QMEMCTRL3 Register
  2134
- QMEMCTRL3 Register Field Descriptions
  2134
- QMEMRBASE4 Register
  2135
- QMEMRBASE4 Register Field Descriptions
  2135
- QMEMCTRL4 Register
  2136
- QMEMCTRL4 Register Field Descriptions
  2136
- QMEMRBASE5 Register
  2137
- QMEMRBASE5 Register Field Descriptions
  2137
- QMEMCTRL5 Register
  2138
- QMEMCTRL5 Register Field Descriptions
  2138
- QMEMRBASE6 Register
  2139
- QMEMRBASE6 Register Field Descriptions
  2139
- QMEMCTRL6 Register
  2140
- QMEMCTRL6 Register Field Descriptions
  2140
- QMEMRBASE7 Register
  2141
- QMEMRBASE7 Register Field Descriptions
  2141
- QMEMCTRL7 Register
  2142
- QMEMCTRL7 Register Field Descriptions
  2142
- QUEUE_0_A Register
  2143
- QUEUE_0_B Register
  2144
- QUEUE_0_C Register
  2145
- QUEUE_0_D Register
  2146
- QUEUE_1_A Register
  2147
- QUEUE_1_B Register
  2148
- QUEUE_1_C Register
  2149
- QUEUE_1_D Register
  2150
- QUEUE_2_A Register
  2151
- QUEUE_2_B Register
  2152
- QUEUE_2_C Register
  2153
- QUEUE_2_D Register
  2154
- QUEUE_3_A Register
  2155
- QUEUE_3_B Register
  2156
- QUEUE_3_C Register
  2157
- QUEUE_3_D Register
  2158
- QUEUE_4_A Register
  2159
- QUEUE_4_B Register
  2160
- QUEUE_4_C Register
  2161
- QUEUE_4_D Register
  2162
- QUEUE_5_A Register
  2163
- QUEUE_5_B Register
  2164
- QUEUE_5_C Register
  2165
- QUEUE_5_D Register
  2166
- QUEUE_6_A Register
  2167
- QUEUE_6_B Register
  2168
- QUEUE_6_C Register
  2169
- QUEUE_6_D Register
  2170
- QUEUE_7_A Register
  2171
- QUEUE_7_B Register
  2172
- QUEUE_7_C Register
  2173
- QUEUE_7_D Register
  2174
- QUEUE_8_A Register
  2175
- QUEUE_8_B Register
  2176
- QUEUE_8_C Register
  2177
- QUEUE_8_D Register
  2178
- QUEUE_9_A Register
  2179
- QUEUE_9_B Register
  2180
- QUEUE_9_C Register
  2181
- QUEUE_9_D Register
  2182
- QUEUE_10_A Register
  2183
- QUEUE_10_B Register
  2184
- QUEUE_10_C Register
  2185
- QUEUE_10_D Register
  2186
- QUEUE_11_A Register
  2187
- QUEUE_11_B Register
  2188
- QUEUE_11_C Register
  2189
- QUEUE_11_D Register
  2190
- QUEUE_12_A Register
  2191
- QUEUE_12_B Register
  2192
- QUEUE_12_C Register
  2193
- QUEUE_12_D Register
  2194
- QUEUE_13_A Register
  2195
- QUEUE_13_B Register
  2196
- QUEUE_13_C Register
  2197
- QUEUE_13_D Register
  2198
- QUEUE_14_A Register
  2199
- QUEUE_14_B Register
  2200
- QUEUE_14_C Register
  2201
- QUEUE_14_D Register
  2202
- QUEUE_15_A Register
  2203
- QUEUE_15_B Register
  2204
- QUEUE_15_C Register
  2205
- QUEUE_15_D Register
  2206
- QUEUE_16_A Register
  2207
- QUEUE_16_B Register
  2208
- QUEUE_16_C Register
  2209
- QUEUE_16_D Register
  2210
- QUEUE_17_A Register
  2211
- QUEUE_17_B Register
  2212
- QUEUE_17_C Register
  2213
- QUEUE_17_D Register
  2214
- QUEUE_18_A Register
  2215
- QUEUE_18_B Register
  2216
- QUEUE_18_C Register
  2217
- QUEUE_18_D Register
  2218
- QUEUE_19_A Register
  2219
- QUEUE_19_B Register
  2220
- QUEUE_19_C Register
  2221
- QUEUE_19_D Register
  2222
- QUEUE_20_A Register
  2223
- QUEUE_20_B Register
  2224
- QUEUE_20_C Register
  2225
- QUEUE_20_D Register
  2226
- QUEUE_21_A Register
  2227
- QUEUE_21_B Register
  2228
- QUEUE_21_C Register
  2229
- QUEUE_21_D Register
  2230
- QUEUE_22_A Register
  2231
- QUEUE_22_B Register
  2232
- QUEUE_22_C Register
  2233
- QUEUE_22_D Register
  2234
- QUEUE_23_A Register
  2235
- QUEUE_23_B Register
  2236
- QUEUE_23_C Register
  2237
- QUEUE_23_D Register
  2238
- QUEUE_24_A Register
  2239
- QUEUE_24_B Register
  2240
- QUEUE_24_C Register
  2241
- QUEUE_24_D Register
  2242
- QUEUE_25_A Register
  2243
- QUEUE_25_B Register
  2244
- QUEUE_25_C Register
  2245
- QUEUE_25_D Register
  2246
- QUEUE_26_A Register
  2247
- QUEUE_26_B Register
  2248
- QUEUE_26_C Register
  2249
- QUEUE_26_D Register
  2250
- QUEUE_27_A Register
  2251
- QUEUE_27_B Register
  2252
- QUEUE_27_C Register
  2253
- QUEUE_27_D Register
  2254
- QUEUE_28_A Register
  2255
- QUEUE_28_B Register
  2256
- QUEUE_28_C Register
  2257
- QUEUE_28_D Register
  2258
- QUEUE_29_A Register
  2259
- QUEUE_29_B Register
  2260
- QUEUE_29_C Register
  2261
- QUEUE_29_D Register
  2262
- QUEUE_30_A Register
  2263
- QUEUE_30_B Register
  2264
- QUEUE_30_C Register
  2265
- QUEUE_30_D Register
  2266
- QUEUE_31_A Register
  2267
- QUEUE_31_B Register
  2268
- QUEUE_31_C Register
  2269
- QUEUE_31_D Register
  2270
- QUEUE_32_A Register
  2271
- QUEUE_32_B Register
  2272
- QUEUE_32_C Register
  2273
- QUEUE_32_D Register
  2274
- QUEUE_33_A Register
  2275
- QUEUE_33_B Register
  2276
- QUEUE_33_C Register
  2277
- QUEUE_33_D Register
  2278
- QUEUE_34_A Register
  2279
- QUEUE_34_B Register
  2280
- QUEUE_34_C Register
  2281
- QUEUE_34_D Register
  2282
- QUEUE_35_A Register
  2283
- QUEUE_35_B Register
  2284
- QUEUE_35_C Register
  2285
- QUEUE_35_D Register
  2286
- QUEUE_36_A Register
  2287
- QUEUE_36_B Register
  2288
- QUEUE_36_C Register
  2289
- QUEUE_36_D Register
  2290
- QUEUE_37_A Register
  2291
- QUEUE_37_B Register
  2292
- QUEUE_37_C Register
  2293
- QUEUE_37_D Register
  2294
- QUEUE_38_A Register
  2295
- QUEUE_38_B Register
  2296
- QUEUE_38_C Register
  2297
- QUEUE_38_D Register
  2298
- QUEUE_39_A Register
  2299
- QUEUE_39_B Register
  2300
- QUEUE_39_C Register
  2301
- QUEUE_39_D Register
  2302
- QUEUE_40_A Register
  2303
- QUEUE_40_B Register
  2304
- QUEUE_40_C Register
  2305
- QUEUE_40_D Register
  2306
- QUEUE_41_A Register
  2307
- QUEUE_41_B Register
  2308
- QUEUE_41_C Register
  2309
- QUEUE_41_D Register
  2310
- QUEUE_42_A Register
  2311
- QUEUE_42_B Register
  2312
- QUEUE_42_C Register
  2313
- QUEUE_42_D Register
  2314
- QUEUE_43_A Register
  2315
- QUEUE_43_B Register
  2316
- QUEUE_43_C Register
  2317
- QUEUE_43_D Register
  2318
- QUEUE_44_A Register
  2319
- QUEUE_44_B Register
  2320
- QUEUE_44_C Register
  2321
- QUEUE_44_D Register
  2322
- QUEUE_45_A Register
  2323
- QUEUE_45_B Register
  2324
- QUEUE_45_C Register
  2325
- QUEUE_45_D Register
  2326
- QUEUE_46_A Register
  2327
- QUEUE_46_B Register
  2328
- QUEUE_46_C Register
  2329
- QUEUE_46_D Register
  2330
- QUEUE_47_A Register
  2331
- QUEUE_47_B Register
  2332
- QUEUE_47_C Register
  2333
- QUEUE_47_D Register
  2334
- QUEUE_48_A Register
  2335
- QUEUE_48_B Register
  2336
- QUEUE_48_C Register
  2337
- QUEUE_48_D Register
  2338
- QUEUE_49_A Register
  2339
- QUEUE_49_B Register
  2340
- QUEUE_49_C Register
  2341
- QUEUE_49_D Register
  2342
- QUEUE_50_A Register
  2343
- QUEUE_50_B Register
  2344
- QUEUE_50_C Register
  2345
- QUEUE_50_D Register
  2346
- QUEUE_51_A Register
  2347
- QUEUE_51_B Register
  2348
- QUEUE_51_C Register
  2349
- QUEUE_51_D Register
  2350
- QUEUE_52_A Register
  2351
- QUEUE_52_B Register
  2352
- QUEUE_52_C Register
  2353
- QUEUE_52_D Register
  2354
- QUEUE_53_A Register
  2355
- QUEUE_53_B Register
  2356
- QUEUE_53_C Register
  2357
- QUEUE_53_D Register
  2358
- QUEUE_54_A Register
  2359
- QUEUE_54_B Register
  2360
- QUEUE_54_C Register
  2361
- QUEUE_54_D Register
  2362
- QUEUE_55_A Register
  2363
- QUEUE_55_B Register
  2364
- QUEUE_55_C Register
  2365
- QUEUE_55_D Register
  2366
- QUEUE_56_A Register
  2367
- QUEUE_56_B Register
  2368
- QUEUE_56_C Register
  2369
- QUEUE_56_D Register
  2370
- QUEUE_57_A Register
  2371
- QUEUE_57_B Register
  2372
- QUEUE_57_C Register
  2373
- QUEUE_57_D Register
  2374
- QUEUE_58_A Register
  2375
- QUEUE_58_B Register
  2376
- QUEUE_58_C Register
  2377
- QUEUE_58_D Register
  2378
- QUEUE_59_A Register
  2379
- QUEUE_59_B Register
  2380
- QUEUE_59_C Register
  2381
- QUEUE_59_D Register
  2382
- QUEUE_60_A Register
  2383
- QUEUE_60_B Register
  2384
- QUEUE_60_C Register
  2385
- QUEUE_60_D Register
  2386
- QUEUE_61_A Register
  2387
- QUEUE_61_B Register
  2388
- QUEUE_61_C Register
  2389
- QUEUE_61_D Register
  2390
- QUEUE_62_A Register
  2391
- QUEUE_62_B Register
  2392
- QUEUE_62_C Register
  2393
- QUEUE_62_D Register
  2394
- QUEUE_63_A Register
  2395
- QUEUE_63_B Register
  2396
- QUEUE_63_C Register
  2397
- QUEUE_63_D Register
  2398
- QUEUE_64_A Register
  2399
- QUEUE_64_B Register
  2400
- QUEUE_64_C Register
  2401
- QUEUE_64_D Register
  2402
- QUEUE_65_A Register
  2403
- QUEUE_65_B Register
  2404
- QUEUE_65_C Register
  2405
- QUEUE_65_D Register
  2406
- QUEUE_66_A Register
  2407
- QUEUE_66_B Register
  2408
- QUEUE_66_C Register
  2409
- QUEUE_66_D Register
  2410
- QUEUE_67_A Register
  2411
- QUEUE_67_B Register
  2412
- QUEUE_67_C Register
  2413
- QUEUE_67_D Register
  2414
- QUEUE_68_A Register
  2415
- QUEUE_68_B Register
  2416
- QUEUE_68_C Register
  2417
- QUEUE_68_D Register
  2418
- QUEUE_69_A Register
  2419
- QUEUE_69_B Register
  2420
- QUEUE_69_C Register
  2421
- QUEUE_69_D Register
  2422
- QUEUE_70_A Register
  2423
- QUEUE_70_B Register
  2424
- QUEUE_70_C Register
  2425
- QUEUE_70_D Register
  2426
- QUEUE_71_A Register
  2427
- QUEUE_71_B Register
  2428
- QUEUE_71_C Register
  2429
- QUEUE_71_D Register
  2430
- QUEUE_72_A Register
  2431
- QUEUE_72_B Register
  2432
- QUEUE_72_C Register
  2433
- QUEUE_72_D Register
  2434
- QUEUE_73_A Register
  2435
- QUEUE_73_B Register
  2436
- QUEUE_73_C Register
  2437
- QUEUE_73_D Register
  2438
- QUEUE_74_A Register
  2439
- QUEUE_74_B Register
  2440
- QUEUE_74_C Register
  2441
- QUEUE_74_D Register
  2442
- QUEUE_75_A Register
  2443
- QUEUE_75_B Register
  2444
- QUEUE_75_C Register
  2445
- QUEUE_75_D Register
  2446
- QUEUE_76_A Register
  2447
- QUEUE_76_B Register
  2448
- QUEUE_76_C Register
  2449
- QUEUE_76_D Register
  2450
- QUEUE_77_A Register
  2451
- QUEUE_77_B Register
  2452
- QUEUE_77_C Register
  2453
- QUEUE_77_D Register
  2454
- QUEUE_78_A Register
  2455
- QUEUE_78_B Register
  2456
- QUEUE_78_C Register
  2457
- QUEUE_78_D Register
  2458
- QUEUE_79_A Register
  2459
- QUEUE_79_B Register
  2460
- QUEUE_79_C Register
  2461
- QUEUE_79_D Register
  2462
- QUEUE_80_A Register
  2463
- QUEUE_80_B Register
  2464
- QUEUE_80_C Register
  2465
- QUEUE_80_D Register
  2466
- QUEUE_81_A Register
  2467
- QUEUE_81_B Register
  2468
- QUEUE_81_C Register
  2469
- QUEUE_81_D Register
  2470
- QUEUE_82_A Register
  2471
- QUEUE_82_B Register
  2472
- QUEUE_82_C Register
  2473
- QUEUE_82_D Register
  2474
- QUEUE_83_A Register
  2475
- QUEUE_83_B Register
  2476
- QUEUE_83_C Register
  2477
- QUEUE_83_D Register
  2478
- QUEUE_84_A Register
  2479
- QUEUE_84_B Register
  2480
- QUEUE_84_C Register
  2481
- QUEUE_84_D Register
  2482
- QUEUE_85_A Register
  2483
- QUEUE_85_B Register
  2484
- QUEUE_85_C Register
  2485
- QUEUE_85_D Register
  2486
- QUEUE_86_A Register
  2487
- QUEUE_86_B Register
  2488
- QUEUE_86_C Register
  2489
- QUEUE_86_D Register
  2490
- QUEUE_87_A Register
  2491
- QUEUE_87_B Register
  2492
- QUEUE_87_C Register
  2493
- QUEUE_87_D Register
  2494
- QUEUE_88_A Register
  2495
- QUEUE_88_B Register
  2496
- QUEUE_88_C Register
  2497
- QUEUE_88_D Register
  2498
- QUEUE_89_A Register
  2499
- QUEUE_89_B Register
  2500
- QUEUE_89_C Register
  2501
- QUEUE_89_D Register
  2502
- QUEUE_90_A Register
  2503
- QUEUE_90_B Register
  2504
- QUEUE_90_C Register
  2505
- QUEUE_90_D Register
  2506
- QUEUE_91_A Register
  2507
- QUEUE_91_B Register
  2508
- QUEUE_91_C Register
  2509
- QUEUE_91_D Register
  2510
- QUEUE_92_A Register
  2511
- QUEUE_92_B Register
  2512
- QUEUE_92_C Register
  2513
- QUEUE_92_D Register
  2514
- QUEUE_93_A Register
  2515
- QUEUE_93_B Register
  2516
- QUEUE_93_C Register
  2517
- QUEUE_93_D Register
  2518
- QUEUE_94_A Register
  2519
- QUEUE_94_B Register
  2520
- QUEUE_94_C Register
  2521
- QUEUE_94_D Register
  2522
- QUEUE_95_A Register
  2523
- QUEUE_95_B Register
  2524
- QUEUE_95_C Register
  2525
- QUEUE_95_D Register
  2526
- QUEUE_96_A Register
  2527
- QUEUE_96_B Register
  2528
- QUEUE_96_C Register
  2529
- QUEUE_96_D Register
  2530
- QUEUE_97_A Register
  2531
- QUEUE_97_B Register
  2532
- QUEUE_97_C Register
  2533
- QUEUE_97_D Register
  2534
- QUEUE_98_A Register
  2535
- QUEUE_98_B Register
  2536
- QUEUE_98_C Register
  2537
- QUEUE_98_D Register
  2538
- QUEUE_99_A Register
  2539
- QUEUE_99_B Register
  2540
- QUEUE_99_C Register
  2541
- QUEUE_99_D Register
  2542
- QUEUE_100_A Register
  2543
- QUEUE_100_B Register
  2544
- QUEUE_100_C Register
  2545
- QUEUE_100_D Register
  2546
- QUEUE_101_A Register
  2547
- QUEUE_101_B Register
  2548
- QUEUE_101_C Register
  2549
- QUEUE_101_D Register
  2550
- QUEUE_102_A Register
  2551
- QUEUE_102_B Register
  2552
- QUEUE_102_C Register
  2553
- QUEUE_102_C Register Field Descriptions
  2553
- QUEUE_102_D Register
  2554
- QUEUE_102_D Register Field Descriptions
  2554
- QUEUE_103_A Register
  2555
- QUEUE_103_A Register Field Descriptions
  2555
- QUEUE_103_B Register
  2556
- QUEUE_103_B Register Field Descriptions
  2556
- QUEUE_103_C Register
  2557
- QUEUE_103_C Register Field Descriptions
  2557
- QUEUE_103_D Register
  2558
- QUEUE_103_D Register Field Descriptions
  2558
- QUEUE_104_A Register
  2559
- QUEUE_104_A Register Field Descriptions
  2559
- QUEUE_104_B Register
  2560
- QUEUE_104_B Register Field Descriptions
  2560
- QUEUE_104_C Register
  2561
- QUEUE_104_C Register Field Descriptions
  2561
- QUEUE_104_D Register
  2562
- QUEUE_104_D Register Field Descriptions
  2562
- QUEUE_105_A Register
  2563
- QUEUE_105_A Register Field Descriptions
  2563
- QUEUE_105_B Register
  2564
- QUEUE_105_B Register Field Descriptions
  2564
- QUEUE_105_C Register
  2565
- QUEUE_105_C Register Field Descriptions
  2565
- QUEUE_105_D Register
  2566
- QUEUE_105_D Register Field Descriptions
  2566
- QUEUE_106_A Register
  2567
- QUEUE_106_A Register Field Descriptions
  2567
- QUEUE_106_B Register
  2568
- QUEUE_106_B Register Field Descriptions
  2568
- QUEUE_106_C Register
  2569
- QUEUE_106_C Register Field Descriptions
  2569
- QUEUE_106_D Register
  2570
- QUEUE_106_D Register Field Descriptions
  2570
- QUEUE_107_A Register
  2571
- QUEUE_107_A Register Field Descriptions
  2571
- QUEUE_107_B Register
  2572
- QUEUE_107_B Register Field Descriptions
  2572
- QUEUE_107_C Register
  2573
- QUEUE_107_C Register Field Descriptions
  2573
- QUEUE_107_D Register
  2574
- QUEUE_107_D Register Field Descriptions
  2574
- QUEUE_108_A Register
  2575
- QUEUE_108_A Register Field Descriptions
  2575
- QUEUE_108_B Register
  2576
- QUEUE_108_B Register Field Descriptions
  2576
- QUEUE_108_C Register
  2577
- QUEUE_108_C Register Field Descriptions
  2577
- QUEUE_108_D Register
  2578
- QUEUE_108_D Register Field Descriptions
  2578
- QUEUE_109_A Register
  2579
- QUEUE_109_A Register Field Descriptions
  2579
- QUEUE_109_B Register
  2580
- QUEUE_109_B Register Field Descriptions
  2580
- QUEUE_109_C Register
  2581
- QUEUE_109_C Register Field Descriptions
  2581
- QUEUE_109_D Register
  2582
- QUEUE_109_D Register Field Descriptions
  2582
- QUEUE_110_A Register
  2583
- QUEUE_110_A Register Field Descriptions
  2583
- QUEUE_110_B Register
  2584
- QUEUE_110_B Register Field Descriptions
  2584
- QUEUE_110_C Register
  2585
- QUEUE_110_C Register Field Descriptions
  2585
- QUEUE_110_D Register
  2586
- QUEUE_110_D Register Field Descriptions
  2586
- QUEUE_111_A Register
  2587
- QUEUE_111_A Register Field Descriptions
  2587
- QUEUE_111_B Register
  2588
- QUEUE_111_B Register Field Descriptions
  2588
- QUEUE_111_C Register
  2589
- QUEUE_111_C Register Field Descriptions
  2589
- QUEUE_111_D Register
  2590
- QUEUE_111_D Register Field Descriptions
  2590
- QUEUE_112_A Register
  2591
- QUEUE_112_A Register Field Descriptions
  2591
- QUEUE_112_B Register
  2592
- QUEUE_112_B Register Field Descriptions
  2592
- QUEUE_112_C Register
  2593
- QUEUE_112_C Register Field Descriptions
  2593
- QUEUE_112_D Register
  2594
- QUEUE_112_D Register Field Descriptions
  2594
- QUEUE_113_A Register
  2595
- QUEUE_113_A Register Field Descriptions
  2595
- QUEUE_113_B Register
  2596
- QUEUE_113_B Register Field Descriptions
  2596
- QUEUE_113_C Register
  2597
- QUEUE_113_C Register Field Descriptions
  2597
- QUEUE_113_D Register
  2598
- QUEUE_113_D Register Field Descriptions
  2598
- QUEUE_114_A Register
  2599
- QUEUE_114_A Register Field Descriptions
  2599
- QUEUE_114_B Register
  2600
- QUEUE_114_B Register Field Descriptions
  2600
- QUEUE_114_C Register
  2601
- QUEUE_114_C Register Field Descriptions
  2601
- QUEUE_114_D Register
  2602
- QUEUE_114_D Register Field Descriptions
  2602
- QUEUE_115_A Register
  2603
- QUEUE_115_A Register Field Descriptions
  2603
- QUEUE_115_B Register
  2604
- QUEUE_115_B Register Field Descriptions
  2604
- QUEUE_115_C Register
  2605
- QUEUE_115_C Register Field Descriptions
  2605
- QUEUE_115_D Register
  2606
- QUEUE_115_D Register Field Descriptions
  2606
- QUEUE_116_A Register
  2607
- QUEUE_116_A Register Field Descriptions
  2607
- QUEUE_116_B Register
  2608
- QUEUE_116_B Register Field Descriptions
  2608
- QUEUE_116_C Register
  2609
- QUEUE_116_C Register Field Descriptions
  2609
- QUEUE_116_D Register
  2610
- QUEUE_116_D Register Field Descriptions
  2610
- QUEUE_117_A Register
  2611
- QUEUE_117_A Register Field Descriptions
  2611
- QUEUE_117_B Register
  2612
- QUEUE_117_B Register Field Descriptions
  2612
- QUEUE_117_C Register
  2613
- QUEUE_117_C Register Field Descriptions
  2613
- QUEUE_117_D Register
  2614
- QUEUE_117_D Register Field Descriptions
  2614
- QUEUE_118_A Register
  2615
- QUEUE_118_A Register Field Descriptions
  2615
- QUEUE_118_B Register
  2616
- QUEUE_118_B Register Field Descriptions
  2616
- QUEUE_118_C Register
  2617
- QUEUE_118_C Register Field Descriptions
  2617
- QUEUE_118_D Register
  2618
- QUEUE_118_D Register Field Descriptions
  2618
- QUEUE_119_A Register
  2619
- QUEUE_119_A Register Field Descriptions
  2619
- QUEUE_119_B Register
  2620
- QUEUE_119_B Register Field Descriptions
  2620
- QUEUE_119_C Register
  2621
- QUEUE_119_C Register Field Descriptions
  2621
- QUEUE_119_D Register
  2622
- QUEUE_119_D Register Field Descriptions
  2622
- QUEUE_120_A Register
  2623
- QUEUE_120_A Register Field Descriptions
  2623
- QUEUE_120_B Register
  2624
- QUEUE_120_B Register Field Descriptions
  2624
- QUEUE_120_C Register
  2625
- QUEUE_120_C Register Field Descriptions
  2625
- QUEUE_120_D Register
  2626
- QUEUE_120_D Register Field Descriptions
  2626
- QUEUE_121_A Register
  2627
- QUEUE_121_A Register Field Descriptions
  2627
- QUEUE_121_B Register
  2628
- QUEUE_121_B Register Field Descriptions
  2628
- QUEUE_121_C Register
  2629
- QUEUE_121_C Register Field Descriptions
  2629
- QUEUE_121_D Register
  2630
- QUEUE_121_D Register Field Descriptions
  2630
- QUEUE_122_A Register
  2631
- QUEUE_122_A Register Field Descriptions
  2631
- QUEUE_122_B Register
  2632
- QUEUE_122_B Register Field Descriptions
  2632
- QUEUE_122_C Register
  2633
- QUEUE_122_C Register Field Descriptions
  2633
- QUEUE_122_D Register
  2634
- QUEUE_122_D Register Field Descriptions
  2634
- QUEUE_123_A Register
  2635
- QUEUE_123_A Register Field Descriptions
  2635
- QUEUE_123_B Register
  2636
- QUEUE_123_B Register Field Descriptions
  2636
- QUEUE_123_C Register
  2637
- QUEUE_123_C Register Field Descriptions
  2637
- QUEUE_123_D Register
  2638
- QUEUE_123_D Register Field Descriptions
  2638
- QUEUE_124_A Register
  2639
- QUEUE_124_A Register Field Descriptions
  2639
- QUEUE_124_B Register
  2640
- QUEUE_124_B Register Field Descriptions
  2640
- QUEUE_124_C Register
  2641
- QUEUE_124_C Register Field Descriptions
  2641
- QUEUE_124_D Register
  2642
- QUEUE_124_D Register Field Descriptions
  2642
- QUEUE_125_A Register
  2643
- QUEUE_125_A Register Field Descriptions
  2643
- QUEUE_125_B Register
  2644
- QUEUE_125_B Register Field Descriptions
  2644
- QUEUE_125_C Register
  2645
- QUEUE_125_C Register Field Descriptions
  2645
- QUEUE_125_D Register
  2646
- QUEUE_125_D Register Field Descriptions
  2646
- QUEUE_126_A Register
  2647
- QUEUE_126_A Register Field Descriptions
  2647
- QUEUE_126_B Register
  2648
- QUEUE_126_B Register Field Descriptions
  2648
- QUEUE_126_C Register
  2649
- QUEUE_126_C Register Field Descriptions
  2649
- QUEUE_126_D Register
  2650
- QUEUE_126_D Register Field Descriptions
  2650
- QUEUE_127_A Register
  2651
- QUEUE_127_A Register Field Descriptions
  2651
- QUEUE_127_B Register
  2652
- QUEUE_127_B Register Field Descriptions
  2652
- QUEUE_127_C Register
  2653
- QUEUE_127_C Register Field Descriptions
  2653
- QUEUE_127_D Register
  2654
- QUEUE_127_D Register Field Descriptions
  2654
- QUEUE_128_A Register
  2655
- QUEUE_128_A Register Field Descriptions
  2655
- QUEUE_128_B Register
  2656
- QUEUE_128_B Register Field Descriptions
  2656
- QUEUE_128_C Register
  2657
- QUEUE_128_C Register Field Descriptions
  2657
- QUEUE_128_D Register
  2658
- QUEUE_128_D Register Field Descriptions
  2658
- QUEUE_129_A Register
  2659
- QUEUE_129_A Register Field Descriptions
  2659
- QUEUE_129_B Register
  2660
- QUEUE_129_B Register Field Descriptions
  2660
- QUEUE_129_C Register
  2661
- QUEUE_129_C Register Field Descriptions
  2661
- QUEUE_129_D Register
  2662
- QUEUE_129_D Register Field Descriptions
  2662
- QUEUE_130_A Register
  2663
- QUEUE_130_A Register Field Descriptions
  2663
- QUEUE_130_B Register
  2664
- QUEUE_130_B Register Field Descriptions
  2664
- QUEUE_130_C Register
  2665
- QUEUE_130_C Register Field Descriptions
  2665
- QUEUE_130_D Register
  2666
- QUEUE_130_D Register Field Descriptions
  2666
- QUEUE_131_A Register
  2667
- QUEUE_131_A Register Field Descriptions
  2667
- QUEUE_131_B Register
  2668
- QUEUE_131_B Register Field Descriptions
  2668
- QUEUE_131_C Register
  2669
- QUEUE_131_C Register Field Descriptions
  2669
- QUEUE_131_D Register
  2670
- QUEUE_131_D Register Field Descriptions
  2670
- QUEUE_132_A Register
  2671
- QUEUE_132_A Register Field Descriptions
  2671
- QUEUE_132_B Register
  2672
- QUEUE_132_B Register Field Descriptions
  2672
- QUEUE_132_C Register
  2673
- QUEUE_132_C Register Field Descriptions
  2673
- QUEUE_132_D Register
  2674
- QUEUE_132_D Register Field Descriptions
  2674
- QUEUE_133_A Register
  2675
- QUEUE_133_A Register Field Descriptions
  2675
- QUEUE_133_B Register
  2676
- QUEUE_133_B Register Field Descriptions
  2676
- QUEUE_133_C Register
  2677
- QUEUE_133_C Register Field Descriptions
  2677
- QUEUE_133_D Register
  2678
- QUEUE_133_D Register Field Descriptions
  2678
- QUEUE_134_A Register
  2679
- QUEUE_134_A Register Field Descriptions
  2679
- QUEUE_134_B Register
  2680
- QUEUE_134_B Register Field Descriptions
  2680
- QUEUE_134_C Register
  2681
- QUEUE_134_C Register Field Descriptions
  2681
- QUEUE_134_D Register
  2682
- QUEUE_134_D Register Field Descriptions
  2682
- QUEUE_135_A Register
  2683
- QUEUE_135_A Register Field Descriptions
  2683
- QUEUE_135_B Register
  2684
- QUEUE_135_B Register Field Descriptions
  2684
- QUEUE_135_C Register
  2685
- QUEUE_135_C Register Field Descriptions
  2685
- QUEUE_135_D Register
  2686
- QUEUE_135_D Register Field Descriptions
  2686
- QUEUE_136_A Register
  2687
- QUEUE_136_A Register Field Descriptions
  2687
- QUEUE_136_B Register
  2688
- QUEUE_136_B Register Field Descriptions
  2688
- QUEUE_136_C Register
  2689
- QUEUE_136_C Register Field Descriptions
  2689
- QUEUE_136_D Register
  2690
- QUEUE_136_D Register Field Descriptions
  2690
- QUEUE_137_A Register
  2691
- QUEUE_137_A Register Field Descriptions
  2691
- QUEUE_137_B Register
  2692
- QUEUE_137_B Register Field Descriptions
  2692
- QUEUE_137_C Register
  2693
- QUEUE_137_C Register Field Descriptions
  2693
- QUEUE_137_D Register
  2694
- QUEUE_137_D Register Field Descriptions
  2694
- QUEUE_138_A Register
  2695
- QUEUE_138_A Register Field Descriptions
  2695
- QUEUE_138_B Register
  2696
- QUEUE_138_B Register Field Descriptions
  2696
- QUEUE_138_C Register
  2697
- QUEUE_138_C Register Field Descriptions
  2697
- QUEUE_138_D Register
  2698
- QUEUE_138_D Register Field Descriptions
  2698
- QUEUE_139_A Register
  2699
- QUEUE_139_A Register Field Descriptions
  2699
- QUEUE_139_B Register
  2700
- QUEUE_139_B Register Field Descriptions
  2700
- QUEUE_139_C Register
  2701
- QUEUE_139_C Register Field Descriptions
  2701
- QUEUE_139_D Register
  2702
- QUEUE_139_D Register Field Descriptions
  2702
- QUEUE_140_A Register
  2703
- QUEUE_140_A Register Field Descriptions
  2703
- QUEUE_140_B Register
  2704
- QUEUE_140_B Register Field Descriptions
  2704
- QUEUE_140_C Register
  2705
- QUEUE_140_C Register Field Descriptions
  2705
- QUEUE_140_D Register
  2706
- QUEUE_140_D Register Field Descriptions
  2706
- QUEUE_141_A Register
  2707
- QUEUE_141_A Register Field Descriptions
  2707
- QUEUE_141_B Register
  2708
- QUEUE_141_B Register Field Descriptions
  2708
- QUEUE_141_C Register
  2709
- QUEUE_141_C Register Field Descriptions
  2709
- QUEUE_141_D Register
  2710
- QUEUE_141_D Register Field Descriptions
  2710
- QUEUE_142_A Register
  2711
- QUEUE_142_A Register Field Descriptions
  2711
- QUEUE_142_B Register
  2712
- QUEUE_142_B Register Field Descriptions
  2712
- QUEUE_142_C Register
  2713
- QUEUE_142_C Register Field Descriptions
  2713
- QUEUE_142_D Register
  2714
- QUEUE_142_D Register Field Descriptions
  2714
- QUEUE_143_A Register
  2715
- QUEUE_143_A Register Field Descriptions
  2715
- QUEUE_143_B Register
  2716
- QUEUE_143_B Register Field Descriptions
  2716
- QUEUE_143_C Register
  2717
- QUEUE_143_C Register Field Descriptions
  2717
- QUEUE_143_D Register
  2718
- QUEUE_143_D Register Field Descriptions
  2718
- QUEUE_144_A Register
  2719
- QUEUE_144_A Register Field Descriptions
  2719
- QUEUE_144_B Register
  2720
- QUEUE_144_B Register Field Descriptions
  2720
- QUEUE_144_C Register
  2721
- QUEUE_144_C Register Field Descriptions
  2721
- QUEUE_144_D Register
  2722
- QUEUE_144_D Register Field Descriptions
  2722
- QUEUE_145_A Register
  2723
- QUEUE_145_A Register Field Descriptions
  2723
- QUEUE_145_B Register
  2724
- QUEUE_145_B Register Field Descriptions
  2724
- QUEUE_145_C Register
  2725
- QUEUE_145_C Register Field Descriptions
  2725
- QUEUE_145_D Register
  2726
- QUEUE_145_D Register Field Descriptions
  2726
- QUEUE_146_A Register
  2727
- QUEUE_146_A Register Field Descriptions
  2727
- QUEUE_146_B Register
  2728
- QUEUE_146_B Register Field Descriptions
  2728
- QUEUE_146_C Register
  2729
- QUEUE_146_C Register Field Descriptions
  2729
- QUEUE_146_D Register
  2730
- QUEUE_146_D Register Field Descriptions
  2730
- QUEUE_147_A Register
  2731
- QUEUE_147_A Register Field Descriptions
  2731
- QUEUE_147_B Register
  2732
- QUEUE_147_B Register Field Descriptions
  2732
- QUEUE_147_C Register
  2733
- QUEUE_147_C Register Field Descriptions
  2733
- QUEUE_147_D Register
  2734
- QUEUE_147_D Register Field Descriptions
  2734
- QUEUE_148_A Register
  2735
- QUEUE_148_A Register Field Descriptions
  2735
- QUEUE_148_B Register
  2736
- QUEUE_148_B Register Field Descriptions
  2736
- QUEUE_148_C Register
  2737
- QUEUE_148_C Register Field Descriptions
  2737
- QUEUE_148_D Register
  2738
- QUEUE_148_D Register Field Descriptions
  2738
- QUEUE_149_A Register
  2739
- QUEUE_149_A Register Field Descriptions
  2739
- QUEUE_149_B Register
  2740
- QUEUE_149_B Register Field Descriptions
  2740
- QUEUE_149_C Register
  2741
- QUEUE_149_C Register Field Descriptions
  2741
- QUEUE_149_D Register
  2742
- QUEUE_149_D Register Field Descriptions
  2742
- QUEUE_150_A Register
  2743
- QUEUE_150_A Register Field Descriptions
  2743
- QUEUE_150_B Register
  2744
- QUEUE_150_B Register Field Descriptions
  2744
- QUEUE_150_C Register
  2745
- QUEUE_150_C Register Field Descriptions
  2745
- QUEUE_150_D Register
  2746
- QUEUE_150_D Register Field Descriptions
  2746
- QUEUE_151_A Register
  2747
- QUEUE_151_A Register Field Descriptions
  2747
- QUEUE_151_B Register
  2748
- QUEUE_151_B Register Field Descriptions
  2748
- QUEUE_151_C Register
  2749
- QUEUE_151_C Register Field Descriptions
  2749
- QUEUE_151_D Register
  2750
- QUEUE_151_D Register Field Descriptions
  2750
- QUEUE_152_A Register
  2751
- QUEUE_152_A Register Field Descriptions
  2751
- QUEUE_152_B Register
  2752
- QUEUE_152_B Register Field Descriptions
  2752
- QUEUE_152_C Register
  2753
- QUEUE_152_C Register Field Descriptions
  2753
- QUEUE_152_D Register
  2754
- QUEUE_152_D Register Field Descriptions
  2754
- QUEUE_153_A Register
  2755
- QUEUE_153_A Register Field Descriptions
  2755
- QUEUE_153_B Register
  2756
- QUEUE_153_B Register Field Descriptions
  2756
- QUEUE_153_C Register
  2757
- QUEUE_153_C Register Field Descriptions
  2757
- QUEUE_153_D Register
  2758
- QUEUE_153_D Register Field Descriptions
  2758
- QUEUE_154_A Register
  2759
- QUEUE_154_A Register Field Descriptions
  2759
- QUEUE_154_B Register
  2760
- QUEUE_154_B Register Field Descriptions
  2760
- QUEUE_154_C Register
  2761
- QUEUE_154_C Register Field Descriptions
  2761
- QUEUE_154_D Register
  2762
- QUEUE_154_D Register Field Descriptions
  2762
- QUEUE_155_A Register
  2763
- QUEUE_155_A Register Field Descriptions
  2763
- QUEUE_155_B Register
  2764
- QUEUE_155_B Register Field Descriptions
  2764
- QUEUE_155_C Register
  2765
- QUEUE_155_C Register Field Descriptions
  2765
- QUEUE_155_D Register
  2766
- QUEUE_155_D Register Field Descriptions
  2766
- QUEUE_0_STATUS_A Register
  2767
- QUEUE_0_STATUS_B Register
  2768
- QUEUE_0_STATUS_C Register
  2769
- QUEUE_1_STATUS_A Register
  2770
- QUEUE_1_STATUS_B Register
  2771
- QUEUE_1_STATUS_C Register
  2772
- QUEUE_2_STATUS_A Register
  2773
- QUEUE_2_STATUS_B Register
  2774
- QUEUE_2_STATUS_C Register
  2775
- QUEUE_3_STATUS_A Register
  2776
- QUEUE_3_STATUS_B Register
  2777
- QUEUE_3_STATUS_C Register
  2778
- QUEUE_4_STATUS_A Register
  2779
- QUEUE_4_STATUS_B Register
  2780
- QUEUE_4_STATUS_C Register
  2781
- QUEUE_5_STATUS_A Register
  2782
- QUEUE_5_STATUS_B Register
  2783
- QUEUE_5_STATUS_C Register
  2784
- QUEUE_6_STATUS_A Register
  2785
- QUEUE_6_STATUS_B Register
  2786
- QUEUE_6_STATUS_C Register
  2787
- QUEUE_7_STATUS_A Register
  2788
- QUEUE_7_STATUS_B Register
  2789
- QUEUE_7_STATUS_C Register
  2790
- QUEUE_8_STATUS_A Register
  2791
- QUEUE_8_STATUS_B Register
  2792
- QUEUE_8_STATUS_C Register
  2793
- QUEUE_9_STATUS_A Register
  2794
- QUEUE_9_STATUS_B Register
  2795
- QUEUE_9_STATUS_C Register
  2796
- QUEUE_10_STATUS_A Register
  2797
- QUEUE_10_STATUS_B Register
  2798
- QUEUE_10_STATUS_C Register
  2799
- QUEUE_11_STATUS_A Register
  2800
- QUEUE_11_STATUS_B Register
  2801
- QUEUE_11_STATUS_C Register
  2802
- QUEUE_12_STATUS_A Register
  2803
- QUEUE_12_STATUS_B Register
  2804
- QUEUE_12_STATUS_C Register
  2805
- QUEUE_13_STATUS_A Register
  2806
- QUEUE_13_STATUS_B Register
  2807
- QUEUE_13_STATUS_C Register
  2808
- QUEUE_14_STATUS_A Register
  2809
- QUEUE_14_STATUS_B Register
  2810
- QUEUE_14_STATUS_C Register
  2811
- QUEUE_15_STATUS_A Register
  2812
- QUEUE_15_STATUS_B Register
  2813
- QUEUE_15_STATUS_C Register
  2814
- QUEUE_16_STATUS_A Register
  2815
- QUEUE_16_STATUS_B Register
  2816
- QUEUE_16_STATUS_C Register
  2817
- QUEUE_17_STATUS_A Register
  2818
- QUEUE_17_STATUS_B Register
  2819
- QUEUE_17_STATUS_C Register
  2820
- QUEUE_18_STATUS_A Register
  2821
- QUEUE_18_STATUS_B Register
  2822
- QUEUE_18_STATUS_C Register
  2823
- QUEUE_19_STATUS_A Register
  2824
- QUEUE_19_STATUS_B Register
  2825
- QUEUE_19_STATUS_C Register
  2826
- QUEUE_20_STATUS_A Register
  2827
- QUEUE_20_STATUS_B Register
  2828
- QUEUE_20_STATUS_C Register
  2829
- QUEUE_21_STATUS_A Register
  2830
- QUEUE_21_STATUS_B Register
  2831
- QUEUE_21_STATUS_C Register
  2832
- QUEUE_22_STATUS_A Register
  2833
- QUEUE_22_STATUS_B Register
  2834
- QUEUE_22_STATUS_C Register
  2835
- QUEUE_23_STATUS_A Register
  2836
- QUEUE_23_STATUS_B Register
  2837
- QUEUE_23_STATUS_C Register
  2838
- QUEUE_24_STATUS_A Register
  2839
- QUEUE_24_STATUS_B Register
  2840
- QUEUE_24_STATUS_C Register
  2841
- QUEUE_25_STATUS_A Register
  2842
- QUEUE_25_STATUS_B Register
  2843
- QUEUE_25_STATUS_C Register
  2844
- QUEUE_26_STATUS_A Register
  2845
- QUEUE_26_STATUS_B Register
  2846
- QUEUE_26_STATUS_C Register
  2847
- QUEUE_27_STATUS_A Register
  2848
- QUEUE_27_STATUS_B Register
  2849
- QUEUE_27_STATUS_C Register
  2850
- QUEUE_28_STATUS_A Register
  2851
- QUEUE_28_STATUS_B Register
  2852
- QUEUE_28_STATUS_C Register
  2853
- QUEUE_29_STATUS_A Register
  2854
- QUEUE_29_STATUS_B Register
  2855
- QUEUE_29_STATUS_C Register
  2856
- QUEUE_30_STATUS_A Register
  2857
- QUEUE_30_STATUS_B Register
  2858
- QUEUE_30_STATUS_C Register
  2859
- QUEUE_31_STATUS_A Register
  2860
- QUEUE_31_STATUS_B Register
  2861
- QUEUE_31_STATUS_C Register
  2862
- QUEUE_32_STATUS_A Register
  2863
- QUEUE_32_STATUS_B Register
  2864
- QUEUE_32_STATUS_C Register
  2865
- QUEUE_33_STATUS_A Register
  2866
- QUEUE_33_STATUS_B Register
  2867
- QUEUE_33_STATUS_C Register
  2868
- QUEUE_34_STATUS_A Register
  2869
- QUEUE_34_STATUS_B Register
  2870
- QUEUE_34_STATUS_C Register
  2871
- QUEUE_35_STATUS_A Register
  2872
- QUEUE_35_STATUS_B Register
  2873
- QUEUE_35_STATUS_C Register
  2874
- QUEUE_36_STATUS_A Register
  2875
- QUEUE_36_STATUS_B Register
  2876
- QUEUE_36_STATUS_C Register
  2877
- QUEUE_37_STATUS_A Register
  2878
- QUEUE_37_STATUS_B Register
  2879
- QUEUE_37_STATUS_C Register
  2880
- QUEUE_38_STATUS_A Register
  2881
- QUEUE_38_STATUS_B Register
  2882
- QUEUE_38_STATUS_C Register
  2883
- QUEUE_39_STATUS_A Register
  2884
- QUEUE_39_STATUS_B Register
  2885
- QUEUE_39_STATUS_C Register
  2886
- QUEUE_40_STATUS_A Register
  2887
- QUEUE_40_STATUS_B Register
  2888
- QUEUE_40_STATUS_C Register
  2889
- QUEUE_41_STATUS_A Register
  2890
- QUEUE_41_STATUS_B Register
  2891
- QUEUE_41_STATUS_C Register
  2892
- QUEUE_42_STATUS_A Register
  2893
- QUEUE_42_STATUS_B Register
  2894
- QUEUE_42_STATUS_C Register
  2895
- QUEUE_43_STATUS_A Register
  2896
- QUEUE_43_STATUS_B Register
  2897
- QUEUE_43_STATUS_C Register
  2898
- QUEUE_44_STATUS_A Register
  2899
- QUEUE_44_STATUS_B Register
  2900
- QUEUE_44_STATUS_C Register
  2901
- QUEUE_45_STATUS_A Register
  2902
- QUEUE_45_STATUS_B Register
  2903
- QUEUE_45_STATUS_C Register
  2904
- QUEUE_46_STATUS_A Register
  2905
- QUEUE_46_STATUS_B Register
  2906
- QUEUE_46_STATUS_C Register
  2907
- QUEUE_47_STATUS_A Register
  2908
- QUEUE_47_STATUS_B Register
  2909
- QUEUE_47_STATUS_C Register
  2910
- QUEUE_48_STATUS_A Register
  2911
- QUEUE_48_STATUS_B Register
  2912
- QUEUE_48_STATUS_C Register
  2913
- QUEUE_49_STATUS_A Register
  2914
- QUEUE_49_STATUS_B Register
  2915
- QUEUE_49_STATUS_C Register
  2916
- QUEUE_50_STATUS_A Register
  2917
- QUEUE_50_STATUS_B Register
  2918
- QUEUE_50_STATUS_C Register
  2919
- QUEUE_51_STATUS_A Register
  2920
- QUEUE_51_STATUS_B Register
  2921
- QUEUE_51_STATUS_C Register
  2922
- QUEUE_52_STATUS_A Register
  2923
- QUEUE_52_STATUS_B Register
  2924
- QUEUE_52_STATUS_C Register
  2925
- QUEUE_53_STATUS_A Register
  2926
- QUEUE_53_STATUS_B Register
  2927
- QUEUE_53_STATUS_C Register
  2928
- QUEUE_54_STATUS_A Register
  2929
- QUEUE_54_STATUS_B Register
  2930
- QUEUE_54_STATUS_C Register
  2931
- QUEUE_55_STATUS_A Register
  2932
- QUEUE_55_STATUS_B Register
  2933
- QUEUE_55_STATUS_C Register
  2934
- QUEUE_56_STATUS_A Register
  2935
- QUEUE_56_STATUS_B Register
  2936
- QUEUE_56_STATUS_C Register
  2937
- QUEUE_57_STATUS_A Register
  2938
- QUEUE_57_STATUS_B Register
  2939
- QUEUE_57_STATUS_C Register
  2940
- QUEUE_58_STATUS_A Register
  2941
- QUEUE_58_STATUS_B Register
  2942
- QUEUE_58_STATUS_C Register
  2943
- QUEUE_59_STATUS_A Register
  2944
- QUEUE_59_STATUS_B Register
  2945
- QUEUE_59_STATUS_C Register
  2946
- QUEUE_60_STATUS_A Register
  2947
- QUEUE_60_STATUS_B Register
  2948
- QUEUE_60_STATUS_C Register
  2949
- QUEUE_61_STATUS_A Register
  2950
- QUEUE_61_STATUS_B Register
  2951
- QUEUE_61_STATUS_C Register
  2952
- QUEUE_62_STATUS_A Register
  2953
- QUEUE_62_STATUS_B Register
  2954
- QUEUE_62_STATUS_C Register
  2955
- QUEUE_63_STATUS_A Register
  2956
- QUEUE_63_STATUS_B Register
  2957
- QUEUE_63_STATUS_C Register
  2958
- QUEUE_64_STATUS_A Register
  2959
- QUEUE_64_STATUS_B Register
  2960
- QUEUE_64_STATUS_C Register
  2961
- QUEUE_65_STATUS_A Register
  2962
- QUEUE_65_STATUS_B Register
  2963
- QUEUE_65_STATUS_C Register
  2964
- QUEUE_66_STATUS_A Register
  2965
- QUEUE_66_STATUS_B Register
  2966
- QUEUE_66_STATUS_C Register
  2967
- QUEUE_67_STATUS_A Register
  2968
- QUEUE_67_STATUS_B Register
  2969
- QUEUE_67_STATUS_C Register
  2970
- QUEUE_68_STATUS_A Register
  2971
- QUEUE_68_STATUS_B Register
  2972
- QUEUE_68_STATUS_C Register
  2973
- QUEUE_69_STATUS_A Register
  2974
- QUEUE_69_STATUS_B Register
  2975
- QUEUE_69_STATUS_C Register
  2976
- QUEUE_70_STATUS_A Register
  2977
- QUEUE_70_STATUS_B Register
  2978
- QUEUE_70_STATUS_C Register
  2979
- QUEUE_71_STATUS_A Register
  2980
- QUEUE_71_STATUS_B Register
  2981
- QUEUE_71_STATUS_C Register
  2982
- QUEUE_72_STATUS_A Register
  2983
- QUEUE_72_STATUS_B Register
  2984
- QUEUE_72_STATUS_C Register
  2985
- QUEUE_73_STATUS_A Register
  2986
- QUEUE_73_STATUS_B Register
  2987
- QUEUE_73_STATUS_C Register
  2988
- QUEUE_74_STATUS_A Register
  2989
- QUEUE_74_STATUS_B Register
  2990
- QUEUE_74_STATUS_C Register
  2991
- QUEUE_75_STATUS_A Register
  2992
- QUEUE_75_STATUS_B Register
  2993
- QUEUE_75_STATUS_C Register
  2994
- QUEUE_76_STATUS_A Register
  2995
- QUEUE_76_STATUS_B Register
  2996
- QUEUE_76_STATUS_C Register
  2997
- QUEUE_77_STATUS_A Register
  2998
- QUEUE_77_STATUS_B Register
  2999
- QUEUE_77_STATUS_C Register
  3000
- QUEUE_78_STATUS_A Register
  3001
- QUEUE_78_STATUS_B Register
  3002
- QUEUE_78_STATUS_C Register
  3003
- QUEUE_79_STATUS_A Register
  3004
- QUEUE_79_STATUS_B Register
  3005
- QUEUE_79_STATUS_C Register
  3006
- QUEUE_80_STATUS_A Register
  3007
- QUEUE_80_STATUS_B Register
  3008
- QUEUE_80_STATUS_C Register
  3009
- QUEUE_81_STATUS_A Register
  3010
- QUEUE_81_STATUS_B Register
  3011
- QUEUE_81_STATUS_C Register
  3012
- QUEUE_82_STATUS_A Register
  3013
- QUEUE_82_STATUS_B Register
  3014
- QUEUE_82_STATUS_C Register
  3015
- QUEUE_83_STATUS_A Register
  3016
- QUEUE_83_STATUS_B Register
  3017
- QUEUE_83_STATUS_C Register
  3018
- QUEUE_84_STATUS_A Register
  3019
- QUEUE_84_STATUS_B Register
  3020
- QUEUE_84_STATUS_C Register
  3021
- QUEUE_85_STATUS_A Register
  3022
- QUEUE_85_STATUS_B Register
  3023
- QUEUE_85_STATUS_C Register
  3024
- QUEUE_86_STATUS_A Register
  3025
- QUEUE_86_STATUS_B Register
  3026
- QUEUE_86_STATUS_C Register
  3027
- QUEUE_87_STATUS_A Register
  3028
- QUEUE_87_STATUS_B Register
  3029
- QUEUE_87_STATUS_C Register
  3030
- QUEUE_88_STATUS_A Register
  3031
- QUEUE_88_STATUS_B Register
  3032
- QUEUE_88_STATUS_C Register
  3033
- QUEUE_89_STATUS_A Register
  3034
- QUEUE_89_STATUS_B Register
  3035
- QUEUE_89_STATUS_C Register
  3036
- QUEUE_90_STATUS_A Register
  3037
- QUEUE_90_STATUS_B Register
  3038
- QUEUE_90_STATUS_C Register
  3039
- QUEUE_91_STATUS_A Register
  3040
- QUEUE_91_STATUS_B Register
  3041
- QUEUE_91_STATUS_C Register
  3042
- QUEUE_92_STATUS_A Register
  3043
- QUEUE_92_STATUS_B Register
  3044
- QUEUE_92_STATUS_C Register
  3045
- QUEUE_93_STATUS_A Register
  3046
- QUEUE_93_STATUS_B Register
  3047
- QUEUE_93_STATUS_C Register
  3048
- QUEUE_94_STATUS_A Register
  3049
- QUEUE_94_STATUS_B Register
  3050
- QUEUE_94_STATUS_C Register
  3051
- QUEUE_95_STATUS_A Register
  3052
- QUEUE_95_STATUS_B Register
  3053
- QUEUE_95_STATUS_C Register
  3054
- QUEUE_96_STATUS_A Register
  3055
- QUEUE_96_STATUS_B Register
  3056
- QUEUE_96_STATUS_C Register
  3057
- QUEUE_97_STATUS_A Register
  3058
- QUEUE_97_STATUS_B Register
  3059
- QUEUE_97_STATUS_C Register
  3060
- QUEUE_98_STATUS_A Register
  3061
- QUEUE_98_STATUS_B Register
  3062
- QUEUE_98_STATUS_C Register
  3063
- QUEUE_99_STATUS_A Register
  3064
- QUEUE_99_STATUS_B Register
  3065
- QUEUE_99_STATUS_C Register
  3066
- QUEUE_100_STATUS_A Register
  3067
- QUEUE_100_STATUS_B Register
  3068
- QUEUE_100_STATUS_C Register
  3069
- QUEUE_101_STATUS_A Register
  3070
- QUEUE_101_STATUS_B Register
  3071
- QUEUE_101_STATUS_C Register
  3072
- QUEUE_102_STATUS_A Register
  3073
- QUEUE_102_STATUS_B Register
  3074
- QUEUE_102_STATUS_C Register
  3075
- QUEUE_103_STATUS_A Register
  3076
- QUEUE_103_STATUS_B Register
  3077
- QUEUE_103_STATUS_C Register
  3078
- QUEUE_104_STATUS_A Register
  3079
- QUEUE_104_STATUS_B Register
  3080
- QUEUE_104_STATUS_C Register
  3081
- QUEUE_105_STATUS_A Register
  3082
- QUEUE_105_STATUS_B Register
  3083
- QUEUE_105_STATUS_C Register
  3084
- QUEUE_106_STATUS_A Register
  3085
- QUEUE_106_STATUS_B Register
  3086
- QUEUE_106_STATUS_C Register
  3087
- QUEUE_107_STATUS_A Register
  3088
- QUEUE_107_STATUS_B Register
  3089
- QUEUE_107_STATUS_C Register
  3090
- QUEUE_108_STATUS_A Register
  3091
- QUEUE_108_STATUS_B Register
  3092
- QUEUE_108_STATUS_C Register
  3093
- QUEUE_109_STATUS_A Register
  3094
- QUEUE_109_STATUS_B Register
  3095
- QUEUE_109_STATUS_C Register
  3096
- QUEUE_110_STATUS_A Register
  3097
- QUEUE_110_STATUS_B Register
  3098
- QUEUE_110_STATUS_C Register
  3099
- QUEUE_111_STATUS_A Register
  3100
- QUEUE_111_STATUS_B Register
  3101
- QUEUE_111_STATUS_C Register
  3102
- QUEUE_112_STATUS_A Register
  3103
- QUEUE_112_STATUS_B Register
  3104
- QUEUE_112_STATUS_C Register
  3105
- QUEUE_113_STATUS_A Register
  3106
- QUEUE_113_STATUS_B Register
  3107
- QUEUE_113_STATUS_C Register
  3108
- QUEUE_114_STATUS_A Register
  3109
- QUEUE_114_STATUS_B Register
  3110
- QUEUE_114_STATUS_C Register
  3111
- QUEUE_115_STATUS_A Register
  3112
- QUEUE_115_STATUS_B Register
  3113
- QUEUE_115_STATUS_C Register
  3114
- QUEUE_116_STATUS_A Register
  3115
- QUEUE_116_STATUS_B Register
  3116
- QUEUE_116_STATUS_C Register
  3117
- QUEUE_117_STATUS_A Register
  3118
- QUEUE_117_STATUS_B Register
  3119
- QUEUE_117_STATUS_C Register
  3120
- QUEUE_118_STATUS_A Register
  3121
- QUEUE_118_STATUS_B Register
  3122
- QUEUE_118_STATUS_C Register
  3123
- QUEUE_119_STATUS_A Register
  3124
- QUEUE_119_STATUS_B Register
  3125
- QUEUE_119_STATUS_C Register
  3126
- QUEUE_120_STATUS_A Register
  3127
- QUEUE_120_STATUS_B Register
  3128
- QUEUE_120_STATUS_C Register
  3129
- QUEUE_121_STATUS_A Register
  3130
- QUEUE_121_STATUS_B Register
  3131
- QUEUE_121_STATUS_C Register
  3132
- QUEUE_122_STATUS_A Register
  3133
- QUEUE_122_STATUS_B Register
  3134
- QUEUE_122_STATUS_C Register
  3135
- QUEUE_123_STATUS_A Register
  3136
- QUEUE_123_STATUS_B Register
  3137
- QUEUE_123_STATUS_C Register
  3138
- QUEUE_124_STATUS_A Register
  3139
- QUEUE_124_STATUS_B Register
  3140
- QUEUE_124_STATUS_C Register
  3141
- QUEUE_125_STATUS_A Register
  3142
- QUEUE_125_STATUS_B Register
  3143
- QUEUE_125_STATUS_C Register
  3144
- QUEUE_126_STATUS_A Register
  3145
- QUEUE_126_STATUS_B Register
  3146
- QUEUE_126_STATUS_C Register
  3147
- QUEUE_127_STATUS_A Register
  3148
- QUEUE_127_STATUS_B Register
  3149
- QUEUE_127_STATUS_C Register
  3150
- QUEUE_128_STATUS_A Register
  3151
- QUEUE_128_STATUS_B Register
  3152
- QUEUE_128_STATUS_C Register
  3153
- QUEUE_129_STATUS_A Register
  3154
- QUEUE_129_STATUS_B Register
  3155
- QUEUE_129_STATUS_C Register
  3156
- QUEUE_130_STATUS_A Register
  3157
- QUEUE_130_STATUS_B Register
  3158
- QUEUE_130_STATUS_C Register
  3159
- QUEUE_131_STATUS_A Register
  3160
- QUEUE_131_STATUS_B Register
  3161
- QUEUE_131_STATUS_C Register
  3162
- QUEUE_132_STATUS_A Register
  3163
- QUEUE_132_STATUS_B Register
  3164
- QUEUE_132_STATUS_C Register
  3165
- QUEUE_133_STATUS_A Register
  3166
- QUEUE_133_STATUS_B Register
  3167
- QUEUE_133_STATUS_C Register
  3168
- QUEUE_134_STATUS_A Register
  3169
- QUEUE_134_STATUS_B Register
  3170
- QUEUE_134_STATUS_C Register
  3171
- QUEUE_135_STATUS_A Register
  3172
- QUEUE_135_STATUS_B Register
  3173
- QUEUE_135_STATUS_C Register
  3174
- QUEUE_136_STATUS_A Register
  3175
- QUEUE_136_STATUS_B Register
  3176
- QUEUE_136_STATUS_C Register
  3177
- QUEUE_137_STATUS_A Register
  3178
- QUEUE_137_STATUS_B Register
  3179
- QUEUE_137_STATUS_C Register
  3180
- QUEUE_138_STATUS_A Register
  3181
- QUEUE_138_STATUS_B Register
  3182
- QUEUE_138_STATUS_C Register
  3183
- QUEUE_139_STATUS_A Register
  3184
- QUEUE_139_STATUS_B Register
  3185
- QUEUE_139_STATUS_C Register
  3186
- QUEUE_140_STATUS_A Register
  3187
- QUEUE_140_STATUS_B Register
  3188
- QUEUE_140_STATUS_C Register
  3189
- QUEUE_141_STATUS_A Register
  3190
- QUEUE_141_STATUS_B Register
  3191
- QUEUE_141_STATUS_C Register
  3192
- QUEUE_142_STATUS_A Register
  3193
- QUEUE_142_STATUS_B Register
  3194
- QUEUE_142_STATUS_C Register
  3195
- QUEUE_143_STATUS_A Register
  3196
- QUEUE_143_STATUS_B Register
  3197
- QUEUE_143_STATUS_C Register
  3198
- QUEUE_144_STATUS_A Register
  3199
- QUEUE_144_STATUS_B Register
  3200
- QUEUE_144_STATUS_C Register
  3201
- QUEUE_145_STATUS_A Register
  3202
- QUEUE_145_STATUS_B Register
  3203
- QUEUE_145_STATUS_C Register
  3204
- QUEUE_146_STATUS_A Register
  3205
- QUEUE_146_STATUS_B Register
  3206
- QUEUE_146_STATUS_C Register
  3207
- QUEUE_147_STATUS_A Register
  3208
- QUEUE_147_STATUS_B Register
  3209
- QUEUE_147_STATUS_C Register
  3210
- QUEUE_148_STATUS_A Register
  3211
- QUEUE_148_STATUS_B Register
  3212
- QUEUE_148_STATUS_C Register
  3213
- QUEUE_149_STATUS_A Register
  3214
- QUEUE_149_STATUS_B Register
  3215
- QUEUE_149_STATUS_C Register
  3216
- QUEUE_150_STATUS_A Register
  3217
- QUEUE_150_STATUS_B Register
  3218
- QUEUE_150_STATUS_C Register
  3219
- QUEUE_151_STATUS_A Register
  3220
- QUEUE_151_STATUS_B Register
  3221
- QUEUE_151_STATUS_C Register
  3222
- QUEUE_152_STATUS_A Register
  3223
- QUEUE_152_STATUS_B Register
  3224
- QUEUE_152_STATUS_C Register
  3225
- QUEUE_153_STATUS_A Register
  3226
- QUEUE_153_STATUS_B Register
  3227
- QUEUE_153_STATUS_C Register
  3228
- QUEUE_154_STATUS_A Register
  3229
- QUEUE_154_STATUS_B Register
  3230
- QUEUE_154_STATUS_C Register
  3231
- QUEUE_155_STATUS_A Register
  3232
- QUEUE_155_STATUS_B Register
  3233
- QUEUE_155_STATUS_C Register
  3234
- Mailbox Integration
  3237
- Mailbox Block Diagram
  3239
- Interrupt Events
  3240
- Global Initialization of Surrounding Modules for System Mailbox
  3242
- Mailbox Global Initialization
  3243
- Sending a Message (Interrupt Method)
  3243
- Sending a Message (Polling Method)
  3243
- Events Servicing in Receiving Mode
  3244
- Events Servicing in Sending Mode
  3244
- Receiving a Message (Interrupt Method)
  3244
- Receiving a Message (Polling Method)
  3244
- Mailbox Registers
  3245
- REVISION Register
  3248
- REVISION Register Field Descriptions
  3248
- SYSCONFIG Register
  3249
- SYSCONFIG Register Field Descriptions
  3249
- MESSAGE_0 Register
  3250
- MESSAGE_1 Register
  3251
- MESSAGE_2 Register
  3252
- MESSAGE_3 Register
  3253
- MESSAGE_4 Register
  3254
- MESSAGE_5 Register
  3255
- MESSAGE_6 Register
  3256
- MESSAGE_7 Register
  3257
- FIFOSTATUS_0 Register
  3258
- FIFOSTATUS_1 Register
  3259
- FIFOSTATUS_2 Register
  3260
- FIFOSTATUS_3 Register
  3261
- FIFOSTATUS_4 Register
  3262
- FIFOSTATUS_5 Register
  3263
- FIFOSTATUS_6 Register
  3264
- FIFOSTATUS_7 Register
  3265
- MSGSTATUS_0 Register
  3266
- MSGSTATUS_1 Register
  3267
- MSGSTATUS_2 Register
  3268
- MSGSTATUS_3 Register
  3269
- MSGSTATUS_4 Register
  3270
- MSGSTATUS_5 Register
  3271
- MSGSTATUS_6 Register
  3272
- MSGSTATUS_7 Register
  3273
- IRQSTATUS_RAW_0 Register
  3274
- IRQSTATUS_RAW_0 Register Field Descriptions
  3275
- IRQSTATUS_CLR_0 Register
  3276
- IRQSTATUS_CLR_0 Register Field Descriptions
  3277
- IRQENABLE_SET_0 Register
  3278
- IRQENABLE_SET_0 Register Field Descriptions
  3279
- IRQENABLE_CLR_0 Register
  3280
- IRQENABLE_CLR_0 Register Field Descriptions
  3281
- IRQSTATUS_RAW_1 Register
  3282
- IRQSTATUS_RAW_1 Register Field Descriptions
  3283
- IRQSTATUS_CLR_1 Register
  3284
- IRQSTATUS_CLR_1 Register Field Descriptions
  3285
- IRQENABLE_SET_1 Register
  3286
- IRQENABLE_SET_1 Register Field Descriptions
  3287
- IRQENABLE_CLR_1 Register
  3288
- IRQENABLE_CLR_1 Register Field Descriptions
  3289
- IRQSTATUS_RAW_2 Register
  3290
- IRQSTATUS_RAW_2 Register Field Descriptions
  3291
- IRQSTATUS_CLR_2 Register
  3292
- IRQSTATUS_CLR_2 Register Field Descriptions
  3293
- IRQENABLE_SET_2 Register
  3294
- IRQENABLE_SET_2 Register Field Descriptions
  3295
- IRQENABLE_CLR_2 Register
  3296
- IRQENABLE_CLR_2 Register Field Descriptions
  3297
- IRQSTATUS_RAW_3 Register
  3298
- IRQSTATUS_RAW_3 Register Field Descriptions
  3299
- IRQSTATUS_CLR_3 Register
  3300
- IRQSTATUS_CLR_3 Register Field Descriptions
  3301
- IRQENABLE_SET_3 Register
  3302
- IRQENABLE_SET_3 Register Field Descriptions
  3303
- IRQENABLE_CLR_3 Register
  3304
- IRQENABLE_CLR_3 Register Field Descriptions
  3305
- Spinlock Registers
  3306
- REV Register
  3309
- REV Register Field Descriptions
  3309
- SYSCONFIG Register
  3310
- SYSCONFIG Register Field Descriptions
  3310
- SYSTATUS Register
  3311
- SYSTATUS Register Field Descriptions
  3311
- LOCK_REG_0 Register
  3312
- LOCK_REG_1 Register
  3313
- LOCK_REG_2 Register
  3314
- LOCK_REG_3 Register
  3315
- LOCK_REG_4 Register
  3316
- LOCK_REG_5 Register
  3317
- LOCK_REG_6 Register
  3318
- LOCK_REG_7 Register
  3319
- LOCK_REG_8 Register
  3320
- LOCK_REG_9 Register
  3321
- LOCK_REG_10 Register
  3322
- LOCK_REG_11 Register
  3323
- LOCK_REG_12 Register
  3324
- LOCK_REG_13 Register
  3325
- LOCK_REG_14 Register
  3326
- LOCK_REG_15 Register
  3327
- LOCK_REG_16 Register
  3328
- LOCK_REG_17 Register
  3329
- LOCK_REG_18 Register
  3330
- LOCK_REG_19 Register
  3331
- LOCK_REG_20 Register
  3332
- LOCK_REG_21 Register
  3333
- LOCK_REG_22 Register
  3334
- LOCK_REG_23 Register
  3335
- LOCK_REG_24 Register
  3336
- LOCK_REG_25 Register
  3337
- LOCK_REG_26 Register
  3338
- LOCK_REG_27 Register
  3339
- LOCK_REG_28 Register
  3340
- LOCK_REG_29 Register
  3341
- LOCK_REG_30 Register
  3342
- LOCK_REG_31 Register
  3343
- Unsupported MMCHS Features
  3345
- MMCHS Module SDIO Application
  3346
- MMCHS SD (4-Bit) Card Application
  3346
- MMCHS Connectivity Attributes
  3347
- MMCHS Module MMC Application
  3347
- DAT Line Direction for Data Transfer Modes
  3348
- MMCHS Clock Signals
  3348
- MMCHS Pin List
  3348
- ADPDATDIROQ and ADPDATDIRLS Signal States
  3349
- MMC/SD0 Connectivity to an MMC/SD Card
  3350
- MMC/SD1/2 Connectivity to an MMC/SD Card
  3350
- MMC/SD/SDIO Controller Pins and Descriptions
  3351
- Sequential Read Operation (MMC Cards Only)
  3353
- Sequential Write Operation (MMC Cards Only)
  3353
- Multiple Block Read Operation (MMC Cards Only)
  3354
- Multiple Block Write Operation (MMC Cards Only)
  3354
- Command Token Format
  3355
- Response Type Summary
  3355
- Data Packet for Block Transfer (1-Bit)
  3356
- Data Packet for Block Transfer (4-Bit)
  3356
- Data Packet for Sequential Transfer (1-Bit)
  3356
- Data Packet for Block Transfer (8-Bit)
  3357
- Clock Activity Settings
  3360
- Local Power Management Features
  3360
- DMA Receive Mode
  3364
- DMA Transmit Mode
  3365
- Buffer Management for a Write
  3367
- Buffer Management for a Read
  3368
- Memory Size, BLEN, and Buffer Relationship
  3368
- MMC, SD, SDIO Responses in the Sd_Rspxx Registers
  3369
- CC and TC Values Upon Error Detected
  3370
- Busy Timeout after Write CRC Status
  3371
- Busy Timeout for R1B, R5B Responses
  3371
- Read Data Timeout
  3372
- Write CRC Status Timeout
  3372
- Boot Acknowledge Timeout When CMD Held Low
  3373
- Boot Acknowledge Timeout When Using CMD0
  3373
- Auto CMD12 Timing During Write Transfer
  3375
- Auto Command 12 Timings During Read Transfer
  3376
- MMC/SD/SDIO Controller Transfer Stop Command Summary
  3377
- Output Driven on Falling Edge
  3378
- Output Driven on Rising Edge
  3379
- Boot Mode with CMD0
  3380
- Boot Mode with CMD Line Tied to
  3381
- MMC/SD/SDIO Hardware Status Features
  3383
- Global Init for Surrounding Modules
  3384
- MMC/SD/SDIO Controller Software Reset Flow
  3385
- MMC/SD/SDIO Controller Wake-Up Configuration
  3385
- MMC/SD/SDIO Controller Bus Configuration Flow
  3386
- MMC/SD/SDIO Controller Card Identification and Selection - Part
  3387
- MMC/SD/SDIO Controller Card Identification and Selection - Part
  3388
- Multimedia_Card Registers
  3389
- SD_SYSCONFIG Register
  3390
- SD_SYSCONFIG Register Field Descriptions
  3390
- SD_SYSSTATUS Register
  3392
- SD_SYSSTATUS Register Field Descriptions
  3392
- SD_CSRE Register
  3393
- SD_CSRE Register Field Descriptions
  3393
- SD_CMD Register
  3394
- SD_SYSTEST Register
  3394
- SD_SYSTEST Register Field Descriptions
  3394
- SD_CON Register
  3398
- SD_CON Register Field Descriptions
  3399
- SD_PWCNT Register
  3402
- SD_PWCNT Register Field Descriptions
  3402
- SD_SDMASA Register
  3403
- SD_SDMASA Register Field Descriptions
  3403
- SD_BLK Register
  3404
- SD_ARG Register
  3405
- SD_CMD Register Field Descriptions
  3407
- SD_RSP10 Register
  3411
- SD_RSP10 Register Field Descriptions
  3411
- SD_RSP32 Register
  3412
- SD_RSP32 Register Field Descriptions
  3412
- SD_RSP54 Register
  3413
- SD_RSP54 Register Field Descriptions
  3413
- SD_RSP76 Register
  3414
- SD_RSP76 Register Field Descriptions
  3414
- SD_DATA Register
  3415
- SD_DATA Register Field Descriptions
  3415
- SD_PSTATE Register
  3416
- SD_PSTATE Register Field Descriptions
  3416
- SD_HCTL Register
  3419
- SD_HCTL Register Field Descriptions
  3419
- SD_SYSCTL Register
  3422
- SD_SYSCTL Register Field Descriptions
  3422
- SD_STAT Register
  3424
- SD_STAT Register Field Descriptions
  3424
- SD_IE Register
  3429
- SD_IE Register Field Descriptions
  3430
- SD_ISE Register
  3432
- SD_ISE Register Field Descriptions
  3433
- SD_AC12 Register
  3435
- SD_AC12 Register Field Descriptions
  3435
- SD_CAPA Register
  3437
- SD_CAPA Register Field Descriptions
  3437
- SD_CUR_CAPA Register
  3439
- SD_CUR_CAPA Register Field Descriptions
  3439
- SD_FE Register
  3440
- SD_FE Register Field Descriptions
  3441
- SD_ADMAES Register
  3442
- SD_ADMAES Register Field Descriptions
  3442
- SD_ADMASAL Register
  3443
- SD_ADMASAL Register Field Descriptions
  3443
- SD_ADMASAH Register
  3444
- SD_ADMASAH Register Field Descriptions
  3444
- SD_REV Register
  3445
- Unsupported UART Features
  3448
- Uart/Irda Module - Irda/Cir Application
  3449
- Uart/Irda Module - UART Application
  3449
- UART0 Connectivity Attributes
  3449
- UART0 Clock Signals
  3450
- UART1-5 Clock Signals
  3450
- UART1-5 Connectivity Attributes
  3450
- Irda Mode Baud and Error Rates
  3451
- UART Mode Baud and Error Rates
  3451
- UART Muxing Control
  3452
- UART Pin List
  3452
- Uart/Irda/Cir Functional Specification Block Diagram
  3454
- Local Power-Management Features
  3456
- UART Mode Interrupts
  3456
- Irda Mode Interrupts
  3457
- CIR Mode Interrupts
  3458
- FIFO Management Registers
  3459
- RX FIFO Trigger Level Setting Summary
  3460
- TX FIFO Trigger Level Setting Summary
  3460
- RX FIFO Interrupt Request Generation
  3461
- TX FIFO Interrupt Request Generation
  3462
- Receive FIFO DMA Request Generation (32 Characters)
  3463
- Transmit FIFO DMA Request Generation (56 Spaces)
  3464
- Transmit FIFO DMA Request Generation (1 Space)
  3465
- Transmit FIFO DMA Request Generation (8 Spaces)
  3465
- DMA Transmission
  3466
- Transmit FIFO DMA Request Generation Using Direct TX DMA Threshold Programming
  3466
- DMA Reception
  3467
- Subconfiguration Mode a Summary
  3468
- Subconfiguration Mode B Summary
  3468
- Suboperational Mode Summary
  3468
- Uart/Irda/Cir Register Access Mode Overview
  3468
- UART Mode Register Overview
  3470
- UART Mode Selection
  3470
- Irda Mode Register Overview
  3471
- CIR Mode Register Overview
  3472
- Baud Rate Generation
  3474
- UART Data Format
  3474
- UART Baud Rate Settings (48-Mhz Clock)
  3475
- UART Parity Bit Encoding
  3475
- UART_EFR[3:0] Software Flow Control Options
  3477
- Irda SIR Frame Format
  3480
- Irda Encoding Mechanism
  3481
- Irda Decoding Mechanism
  3482
- MIR Transmit Frame Format
  3483
- SIR Free Format Mode
  3483
- FIR Transmit Frame Format
  3484
- MIR BAUD Rate Adjustment Mechanism
  3484
- SIP Pulse
  3484
- Baud Rate Generator
  3485
- Irda Baud Rate Settings
  3486
- RC -5 Bit Encoding
  3489
- SIRC Bit Encoding
  3490
- SIRC Packet Format
  3490
- CIR Mode Block Components
  3491
- SIRC Bit Transmission Example
  3491
- CIR Modulation Duty Cycle
  3493
- CIR Pulse Modulation
  3493
- Variable Pulse Duration Definitions
  3495
- UART Registers
  3505
- Receiver Holding Register (RHR)
  3507
- Receiver Holding Register (RHR) Field Descriptions
  3507
- Transmit Holding Register (THR)
  3507
- Transmit Holding Register (THR) Field Descriptions
  3507
- UART Interrupt Enable Register (IER)
  3508
- UART Interrupt Enable Register (IER) Field Descriptions
  3508
- Irda Interrupt Enable Register (IER)
  3509
- Irda Interrupt Enable Register (IER) Field Descriptions
  3509
- CIR Interrupt Enable Register (IER)
  3510
- CIR Interrupt Enable Register (IER) Field Descriptions
  3510
- UART Interrupt Identification Register (IIR)
  3511
- UART Interrupt Identification Register (IIR) Field Descriptions
  3511
- Irda Interrupt Identification Register (IIR)
  3512
- Irda Interrupt Identification Register (IIR) Field Descriptions
  3512
- CIR Interrupt Identification Register (IIR)
  3513
- CIR Interrupt Identification Register (IIR) Field Descriptions
  3513
- FIFO Control Register (FCR)
  3514
- FIFO Control Register (FCR) Field Descriptions
  3514
- Line Control Register (LCR)
  3515
- Line Control Register (LCR) Field Descriptions
  3515
- Modem Control Register (MCR)
  3516
- Modem Control Register (MCR) Field Descriptions
  3516
- UART Line Status Register (LSR)
  3517
- UART Line Status Register (LSR) Field Descriptions
  3517
- Irda Line Status Register (LSR)
  3518
- Irda Line Status Register (LSR) Field Descriptions
  3518
- CIR Line Status Register (LSR)
  3519
- CIR Line Status Register (LSR) Field Descriptions
  3519
- Modem Status Register (MSR)
  3520
- Modem Status Register (MSR) Field Descriptions
  3520
- Scratchpad Register (SPR)
  3521
- Scratchpad Register (SPR) Field Descriptions
  3521
- Transmission Control Register (TCR)
  3521
- Transmission Control Register (TCR) Field Descriptions
  3521
- RX FIFO Trigger Level Setting Summary
  3522
- Trigger Level Register (TLR)
  3522
- Trigger Level Register (TLR) Field Descriptions
  3522
- TX FIFO Trigger Space Setting Summary
  3522
- Mode Definition Register 1 (MDR1)
  3523
- Mode Definition Register 1 (MDR1) Field Descriptions
  3523
- Mode Definition Register 2 (MDR2)
  3524
- Mode Definition Register 2 (MDR2) Field Descriptions
  3524
- RESUME Register
  3525
- RESUME Register Field Descriptions
  3525
- Status FIFO Line Status Register (SFLSR)
  3525
- Status FIFO Line Status Register (SFLSR) Field Descriptions
  3525
- Status FIFO Register High (SFREGH)
  3526
- Status FIFO Register High (SFREGH) Field Descriptions
  3526
- Status FIFO Register Low (SFREGL)
  3526
- Status FIFO Register Low (SFREGL) Field Descriptions
  3526
- BOF Control Register (BLR)
  3527
- BOF Control Register (BLR) Field Descriptions
  3527
- Auxiliary Control Register (ACREG)
  3528
- Auxiliary Control Register (ACREG) Field Descriptions
  3528
- Supplementary Control Register (SCR)
  3529
- Supplementary Control Register (SCR) Field Descriptions
  3529
- Supplementary Status Register (SSR)
  3530
- Supplementary Status Register (SSR) Field Descriptions
  3530
- BOF Length Register (EBLR)
  3531
- BOF Length Register (EBLR) Field Descriptions
  3531
- Module Version Register (MVR)
  3532
- Module Version Register (MVR) Field Descriptions
  3532
- System Configuration Register (SYSC)
  3533
- System Configuration Register (SYSC) Field Descriptions
  3533
- System Status Register (SYSS)
  3533
- System Status Register (SYSS) Field Descriptions
  3533
- Wake-Up Enable Register (WER)
  3534
- Wake-Up Enable Register (WER) Field Descriptions
  3534
- Carrier Frequency Prescaler Register (CFPS)
  3535
- Carrier Frequency Prescaler Register (CFPS) Field Descriptions
  3535
- Divisor Latches High Register (DLH)
  3536
- Divisor Latches High Register (DLH) Field Descriptions
  3536
- Divisor Latches Low Register (DLL)
  3536
- Divisor Latches Low Register (DLL) Field Descriptions
  3536
- Enhanced Feature Register (EFR)
  3537
- Enhanced Feature Register (EFR) Field Descriptions
  3537
- EFR[3:0] Software Flow Control Options
  3538
- XON1/ADDR1 Register
  3538
- XON1/ADDR1 Register Field Descriptions
  3538
- XON2/ADDR2 Register
  3538
- XON2/ADDR2 Register Field Descriptions
  3538
- XOFF1 Register
  3539
- XOFF1 Register Field Descriptions
  3539
- XOFF2 Register
  3539
- XOFF2 Register Field Descriptions
  3539
- Transmit Frame Length High Register (TXFLH)
  3540
- Transmit Frame Length High Register (TXFLH) Field Descriptions
  3540
- Transmit Frame Length Low Register (TXFLL)
  3540
- Transmit Frame Length Low Register (TXFLL) Field Descriptions
  3540
- Received Frame Length High Register (RXFLH)
  3541
- Received Frame Length High Register (RXFLH) Field Descriptions
  3541
- Received Frame Length Low Register (RXFLL)
  3541
- Received Frame Length Low Register (RXFLL) Field Descriptions
  3541
- UART Autobauding Status Register (UASR)
  3542
- UART Autobauding Status Register (UASR) Field Descriptions
  3542
- RXFIFO_LVL Register
  3543
- TXFIFO_LVL Register
  3544
- IER2 Register
  3545
- IER2 Register Field Descriptions
  3545
- ISR2 Register
  3546
- FREQ_SEL Register
  3547
- Mode Definition Register 3 (MDR3) Register
  3548
- Mode Definition Register 3 (MDR3) Register Field Descriptions
  3548
- TX_DMA_THRESHOLD Register
  3549
- TX_DMA_THRESHOLD Register Field Descriptions
  3549
- Timer Block Diagram
  3552
- Timer Resolution and Maximum Range
  3552
- Timer0 Integration
  3553
- Timer2-7 Integration
  3554
- Timer[0] Connectivity Attributes
  3554
- Timer Clock Signals
  3555
- Timer[2-7] Connectivity Attributes
  3555
- Timer Pin List
  3556
- TCRR Timing Value
  3557
- Capture Wave Example for CAPT_MODE
  3558
- Capture Wave Example for CAPT_MODE
  3559
- Prescaler Functionality
  3559
- Timing Diagram of Pulse-Width Modulation with SCPWM
  3560
- Timing Diagram of Pulse-Width Modulation with SCPWM
  3561
- Prescaler Clock Ratios Value
  3562
- Value and Corresponding Interrupt Period
  3562
- OCP Error Reporting
  3563
- Timer Registers
  3566
- TIDR Register
  3567
- TIDR Register Field Descriptions
  3567
- TIOCP_CFG Register
  3568
- IRQ_EOI Register
  3569
- IRQSTATUS_RAW Register
  3570
- IRQSTATUS Register
  3571
- IRQENABLE_SET Register
  3572
- IRQENABLE_CLR Register
  3573
- IRQWAKEEN Register
  3574
- IRQWAKEEN Register Field Descriptions
  3574
- TCLR Register
  3575
- TCLR Register Field Descriptions
  3575
- TCLR Register Field Descriptions
  3576
- TCRR Register
  3577
- TCRR Register Field Descriptions
  3577
- TLDR Register
  3578
- TLDR Register Field Descriptions
  3578
- TTGR Register
  3579
- TTGR Register Field Descriptions
  3579
- TWPS Register
  3580
- TWPS Register Field Descriptions
  3580
- TMAR Register
  3581
- TMAR Register Field Descriptions
  3581
- TCAR1 Register
  3582
- TCAR1 Register Field Descriptions
  3582
- TSICR Register
  3583
- TSICR Register Field Descriptions
  3583
- TCAR2 Register
  3584
- TCAR2 Register Field Descriptions
  3584
- Block Diagram
  3586
- Dmtimer 1 Ms Integration
  3587
- Timer1 Connectivity Attributes
  3587
- Timer Clock Signals
  3588
- 1Ms Module Block Diagram
  3590
- Value Loaded in TCRR to Generate 1Ms Tick
  3590
- Prescaler/Timer Reload Values Versus Contexts
  3593
- Smartidle - Clock Activity Field Configuration
  3595
- Prescaler Clock Ratios Value
  3596
- Wake-Up Request Generation
  3596
- Dmtimer_1Ms Registers
  3597
- Value and Corresponding Interrupt Period
  3597
- TIDR Register
  3599
- TIDR Register Field Descriptions
  3599
- TIOCP_CFG Register
  3600
- TISTAT Register
  3601
- TISTAT Register Field Descriptions
  3601
- TISR Register
  3602
- TISR Register Field Descriptions
  3602
- TIER Register
  3603
- TIER Register Field Descriptions
  3603
- TWER Register
  3604
- TWER Register Field Descriptions
  3604
- TCLR Register
  3605
- TCRR Register
  3607
- TCRR Register Field Descriptions
  3607
- TLDR Register
  3608
- TLDR Register Field Descriptions
  3608
- TTGR Register
  3609
- TTGR Register Field Descriptions
  3609
- TWPS Register
  3610
- TWPS Register Field Descriptions
  3610
- TMAR Register
  3612
- TMAR Register Field Descriptions
  3612
- TCAR1 Register
  3613
- TCAR1 Register Field Descriptions
  3613
- TSICR Register
  3614
- TSICR Register Field Descriptions
  3614
- TCAR2 Register
  3615
- TCAR2 Register Field Descriptions
  3615
- TPIR Register
  3616
- TPIR Register Field Descriptions
  3616
- TNIR Register
  3617
- TNIR Register Field Descriptions
  3617
- TCVR Register
  3618
- TCVR Register Field Descriptions
  3618
- TOCR Register
  3619
- TOCR Register Field Descriptions
  3619
- TOWR Register
  3620
- TOWR Register Field Descriptions
  3620
- RTC Integration
  3622
- RTC Module Connectivity Attributes
  3622
- RTC Clock Signals
  3623
- RTC Pin List
  3623
- RTC Block Diagram
  3624
- RTC Functional Block Diagram
  3624
- Interrupt Trigger Events
  3625
- RTC Signals
  3625
- Kick Register State Machine Diagram
  3627
- RTC Register Names and Values
  3628
- Flow Control for Updating RTC Registers
  3629
- Compensation Illustration
  3630
- Pmic_Power_En Description
  3631
- Rtc Registers
  3632
- SECONDS_REG Register
  3634
- MINUTES_REG Register
  3635
- HOURS_REG Register
  3636
- DAYS_REG Register
  3637
- MONTHS_REG Register
  3638
- YEARS_REG Register
  3639
- WEEKS_REG Register
  3640
- ALARM_SECONDS_REG Register
  3641
- ALARM_MINUTES_REG Register
  3642
- ALARM_HOURS_REG Register
  3643
- ALARM_DAYS_REG Register
  3644
- ALARM_MONTHS_REG Register
  3645
- ALARM_YEARS_REG Register
  3646
- RTC_CTRL_REG Register
  3647
- RTC_CTRL_REG Register Field Descriptions
  3648
- RTC_STATUS_REG Register
  3649
- RTC_INTERRUPTS_REG Register
  3650
- RTC_COMP_LSB_REG Register
  3651
- RTC_COMP_MSB_REG Register
  3652
- RTC_OSC_REG Register
  3653
- RTC_SCRATCH0_REG Register
  3654
- RTC_SCRATCH1_REG Register
  3655
- RTC_SCRATCH2_REG Register
  3656
- KICK0R Register
  3657
- KICK0R Register Field Descriptions
  3657
- KICK1R Register
  3658
- KICK1R Register Field Descriptions
  3658
- RTC_REVISION Register
  3659
- RTC_REVISION Register Field Descriptions
  3659
- RTC_SYSCONFIG Register
  3660
- RTC_SYSCONFIG Register Field Descriptions
  3660
- RTC_IRQWAKEEN Register
  3661
- RTC_IRQWAKEEN Register Field Descriptions
  3661
- ALARM2_SECONDS_REG Register
  3662
- ALARM2_MINUTES_REG Register
  3663
- ALARM2_HOURS_REG Register
  3664
- ALARM2_DAYS_REG Register
  3665
- ALARM2_MONTHS_REG Register
  3666
- ALARM2_YEARS_REG Register
  3667
- RTC_PMIC Register
  3668
- RTC_PMIC Register Field Descriptions
  3668
- RTC_DEBOUNCE Register
  3669
- RTC_DEBOUNCE Register Field Descriptions
  3669
- Public WD Timer Module Connectivity Attributes
  3671
- Wdtimer Integration
  3671
- Public WD Timer Clock Signals
  3672
- Watchdog Timer Events
  3673
- Count and Prescaler Default Reset Values
  3674
- Watchdog Timers General Functional View
  3674
- Prescaler Clock Ratio Values
  3675
- Reset Period Examples
  3675
- Default Watchdog Timer Reset Periods
  3676
- Global Initialization of Surrounding Modules
  3679
- Watchdog Timer Basic Configuration
  3679
- Watchdog Timer Module Global Initialization
  3679
- Disable the Watchdog Timer
  3680
- Enable the Watchdog Timer
  3680
- Watchdog_Timer Registers
  3680
- WDT_WIDR Register
  3682
- WDT_WIDR Register Field Descriptions
  3682
- WDT_WDSC Register
  3683
- WDT_WDSC Register Field Descriptions
  3683
- WDT_WDST Register
  3684
- WDT_WDST Register Field Descriptions
  3684
- WDT_WISR Register
  3685
- WDT_WISR Register Field Descriptions
  3685
- WDT_WIER Register
  3686
- WDT_WIER Register Field Descriptions
  3686
- WDT_WCLR Register
  3687
- WDT_WCLR Register Field Descriptions
  3687
- WDT_WCRR Register
  3688
- WDT_WCRR Register Field Descriptions
  3688
- WDT_WLDR Register
  3689
- WDT_WLDR Register Field Descriptions
  3689
- WDT_WTGR Register
  3690
- WDT_WTGR Register Field Descriptions
  3690
- WDT_WWPS Register
  3691
- WDT_WWPS Register Field Descriptions
  3691
- WDT_WDLY Register
  3692
- WDT_WDLY Register Field Descriptions
  3692
- WDT_WSPR Register
  3693
- WDT_WSPR Register Field Descriptions
  3693
- WDT_WIRQSTATRAW Register
  3694
- WDT_WIRQSTATRAW Register Field Descriptions
  3694
- WDT_WIRQSTAT Register
  3695
- WDT_WIRQSTAT Register Field Descriptions
  3695
- WDT_WIRQENSET Register
  3696
- WDT_WIRQENSET Register Field Descriptions
  3696
- WDT_WIRQENCLR Register
  3697
- WDT_WIRQENCLR Register Field Descriptions
  3697
- Unsupported I2C Features
  3699
- I2C(1-2) Integration and Bus Application
  3700
- I2C0 Connectivity Attributes
  3700
- I2C0 Integration and Bus Application
  3700
- I2C Clock Signals
  3701
- I2C Pin List
  3701
- I2C(1-2) Connectivity Attributes
  3701
- I2C Functional Block Diagram
  3702
- Multiple I2C Modules Connected
  3703
- Reset State of I2C Signals
  3703
- Signal Pads
  3703
- Bit Transfer on the I2C Bus
  3704
- I2C Data Transfer
  3705
- Start and Stop Condition Events
  3705
- I2C Data Transfer Formats
  3706
- Arbitration Procedure between Two Master Transmitters
  3707
- Synchronization of Two I2C Clock Generators
  3708
- Receive FIFO Interrupt Request Generation
  3710
- Transmit FIFO Interrupt Request Generation
  3710
- Receive FIFO DMA Request Generation
  3711
- Transmit FIFO DMA Request Generation (High Threshold)
  3712
- Transmit FIFO DMA Request Generation (Low Threshold)
  3712
- I2C Registers
  3716
- I2C_REVNB_LO Register
  3717
- I2C_REVNB_HI Register
  3718
- I2C_SYSC Register
  3719
- I2C_SYSC Register Field Descriptions
  3719
- I2C_IRQSTATUS_RAW Register
  3721
- I2C_IRQSTATUS_RAW Register Field Descriptions
  3722
- I2C_IRQSTATUS Register
  3727
- I2C_IRQSTATUS Register Field Descriptions
  3727
- I2C_IRQENABLE_SET Register
  3729
- I2C_IRQENABLE_SET Register Field Descriptions
  3730
- I2C_IRQENABLE_CLR Register
  3731
- I2C_IRQENABLE_CLR Register Field Descriptions
  3731
- I2C_WE Register
  3733
- I2C_WE Register Field Descriptions
  3733
- I2C_DMARXENABLE_SET Register
  3736
- I2C_DMATXENABLE_SET Register
  3737
- I2C_DMARXENABLE_CLR Register
  3738
- I2C_DMATXENABLE_CLR Register
  3739
- I2C_DMARXWAKE_EN Register
  3740
- I2C_DMARXWAKE_EN Register Field Descriptions
  3741
- I2C_DMATXWAKE_EN Register
  3742
- I2C_DMATXWAKE_EN Register Field Descriptions
  3743
- I2C_SYSS Register
  3744
- I2C_SYSS Register Field Descriptions
  3744
- I2C_BUF Register
  3745
- I2C_BUF Register Field Descriptions
  3745
- I2C_CNT Register
  3747
- I2C_CNT Register Field Descriptions
  3747
- I2C_DATA Register
  3748
- I2C_DATA Register Field Descriptions
  3748
- I2C_CON Register
  3749
- I2C_CON Register Field Descriptions
  3749
- I2C_OA Register
  3752
- I2C_OA Register Field Descriptions
  3752
- I2C_SA Register
  3753
- I2C_SA Register Field Descriptions
  3753
- I2C_PSC Register
  3754
- I2C_PSC Register Field Descriptions
  3754
- I2C_SCLL Register
  3755
- I2C_SCLL Register Field Descriptions
  3755
- I2C_SCLH Register
  3756
- I2C_SCLH Register Field Descriptions
  3756
- I2C_SYSTEST Register
  3757
- I2C_SYSTEST Register Field Descriptions
  3757
- I2C_BUFSTAT Register
  3761
- I2C_BUFSTAT Register Field Descriptions
  3761
- I2C_OA1 Register
  3762
- I2C_OA1 Register Field Descriptions
  3762
- I2C_OA2 Register
  3763
- I2C_OA2 Register Field Descriptions
  3763
- I2C_OA3 Register
  3764
- I2C_OA3 Register Field Descriptions
  3764
- I2C_ACTOA Register
  3765
- I2C_ACTOA Register Field Descriptions
  3765
- I2C_SBLOCK Register
  3766
- I2C_SBLOCK Register Field Descriptions
  3766
- Mcasp Connectivity Attributes
  3771
- Mcasp0-1 Integration
  3771
- Mcasp Clock Signals
  3772
- Mcasp Pin List
  3772
- Mcasp Block Diagram
  3774
- Mcasp to 6-Channel DAC and 2-Channel DAC
  3775
- Mcasp to Parallel 2-Channel Dacs
  3775
- Mcasp as 16 Channel Digital Processor
  3776
- Mcasp as Digital Audio Encoder
  3776
- Mcasp to Digital Amplifier
  3776
- TDM Format-6 Channel TDM Example
  3777
- Inter-Integrated Sound (I2S) Format
  3778
- TDM Format Bit Delays from Frame Sync
  3778
- Biphase-Mark Code (BMC)
  3779
- Biphase-Mark Encoder
  3779
- Preamble Codes
  3780
- S/PDIF Subframe Format
  3780
- S/PDIF Frame Format
  3781
- Bit Order and Word Alignment Within a Slot Examples
  3782
- Definition of Bit, Word, and Slot
  3782
- Definition of Frame and Frame Sync Width
  3783
- Transmit Clock Generator Block Diagram
  3784
- Receive Clock Generator Block Diagram
  3785
- Frame Sync Generator Block Diagram
  3786
- Mcasp Interface Signals
  3787
- Burst Frame Sync Mode
  3788
- Transmit DMA Event (AXEVT) Generation in TDM Time Slots
  3790
- Channel Status and User Data for each DIT Block
  3794
- Individual Serializer and Connections Within Mcasp
  3795
- Receive Format Unit
  3796
- Transmit Format Unit
  3796
- Mcasp I/O Pin Control Block Diagram
  3798
- Processor Service Time Upon Transmit DMA Event (AXEVT)
  3800
- Processor Service Time Upon Receive DMA Event (AREVT)
  3801
- Mcasp Audio FIFO (AFIFO) Block Diagram
  3803
- Transmit Bitstream Data Alignment
  3805
- Data Flow through Transmit Format Unit, Illustrated
  3806
- Receive Bitstream Data Alignment
  3807
- Data Flow through Receive Format Unit, Illustrated
  3808
- Transmit Clock Failure Detection Circuit Block Diagram
  3812
- Receive Clock Failure Detection Circuit Block Diagram
  3814
- Serializers in Loopback Mode
  3815
- Interrupt Multiplexing
  3821
- Audio Mute (AMUTE) Block Diagram
  3822
- DMA Events in an Audio Example-Four Events (Scenario 2)
  3824
- DMA Events in an Audio Example-Two Events (Scenario 1)
  3824
- DMA Events in an Audio Example
  3825
- Mcasp Registers Accessed through Configuration Bus
  3826
- Mcasp AFIFO Registers Accessed through Peripheral Configuration Port
  3827
- Revision Identification Register (REV)
  3828
- Revision Identification Register (REV) Field Descriptions
  3828
- Power Idle SYSCONFIG Register (PWRIDLESYSCONFIG)
  3829
- Power Idle SYSCONFIG Register (PWRIDLESYSCONFIG) Field Descriptions
  3829
- Pin Function Register (PFUNC)
  3830
- Pin Function Register (PFUNC) Field Descriptions
  3831
- Pin Direction Register (PDIR)
  3832
- Pin Direction Register (PDIR) Field Descriptions
  3833
- Pin Data Output Register (PDOUT)
  3834
- Pin Data Output Register (PDOUT) Field Descriptions
  3835
- Pin Data Input Register (PDIN)
  3836
- Pin Data Input Register (PDIN) Field Descriptions
  3837
- Pin Data Set Register (PDSET)
  3838
- Pin Data Set Register (PDSET) Field Descriptions
  3839
- Pin Data Clear Register (PDCLR)
  3840
- Pin Data Clear Register (PDCLR) Field Descriptions
  3841
- Global Control Register (GBLCTL)
  3842
- Global Control Register (GBLCTL) Field Descriptions
  3842
- Audio Mute Control Register (AMUTE)
  3844
- Audio Mute Control Register (AMUTE) Field Descriptions
  3844
- Digital Loopback Control Register (DLBCTL)
  3846
- Digital Loopback Control Register (DLBCTL) Field Descriptions
  3846
- Digital Mode Control Register (DITCTL)
  3847
- Digital Mode Control Register (DITCTL) Field Descriptions
  3847
- Receiver Global Control Register (RGBLCTL)
  3848
- Receiver Global Control Register (RGBLCTL) Field Descriptions
  3848
- Receive Format Unit Bit Mask Register (RMASK)
  3849
- Receive Format Unit Bit Mask Register (RMASK) Field Descriptions
  3849
- Receive Bit Stream Format Register (RFMT)
  3850
- Receive Bit Stream Format Register (RFMT) Field Descriptions
  3850
- Receive Frame Sync Control Register (AFSRCTL)
  3852
- Receive Frame Sync Control Register (AFSRCTL) Field Descriptions
  3852
- Receive Clock Control Register (ACLKRCTL)
  3853
- Receive Clock Control Register (ACLKRCTL) Field Descriptions
  3853
- Receive High-Frequency Clock Control Register (AHCLKRCTL)
  3854
- Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions
  3854
- Receive TDM Time Slot Register (RTDM)
  3855
- Receive TDM Time Slot Register (RTDM) Field Descriptions
  3855
- Receiver Interrupt Control Register (RINTCTL)
  3856
- Receiver Interrupt Control Register (RINTCTL) Field Descriptions
  3856
- Receiver Status Register (RSTAT)
  3857
- Receiver Status Register (RSTAT) Field Descriptions
  3857
- Current Receive TDM Time Slot Registers (RSLOT)
  3858
- Current Receive TDM Time Slot Registers (RSLOT) Field Descriptions
  3858
- Receive Clock Check Control Register (RCLKCHK)
  3859
- Receive Clock Check Control Register (RCLKCHK) Field Descriptions
  3859
- Receiver DMA Event Control Register (REVTCTL)
  3860
- Receiver DMA Event Control Register (REVTCTL) Field Descriptions
  3860
- Transmitter Global Control Register (XGBLCTL)
  3861
- Transmitter Global Control Register (XGBLCTL) Field Descriptions
  3861
- Transmit Format Unit Bit Mask Register (XMASK)
  3862
- Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions
  3862
- Transmit Bit Stream Format Register (XFMT)
  3863
- Transmit Bit Stream Format Register (XFMT) Field Descriptions
  3863
- Transmit Frame Sync Control Register (AFSXCTL)
  3865
- Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions
  3865
- Transmit Clock Control Register (ACLKXCTL)
  3866
- Transmit Clock Control Register (ACLKXCTL) Field Descriptions
  3866
- Transmit High-Frequency Clock Control Register (AHCLKXCTL)
  3867
- Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions
  3867
- Transmit TDM Time Slot Register (XTDM)
  3868
- Transmit TDM Time Slot Register (XTDM) Field Descriptions
  3868
- Transmitter Interrupt Control Register (XINTCTL)
  3869
- Transmitter Interrupt Control Register (XINTCTL) Field Descriptions
  3869
- Transmitter Status Register (XSTAT)
  3870
- Transmitter Status Register (XSTAT) Field Descriptions
  3870
- Current Transmit TDM Time Slot Register (XSLOT)
  3871
- Current Transmit TDM Time Slot Register (XSLOT) Field Descriptions
  3871
- Transmit Clock Check Control Register (XCLKCHK)
  3872
- Transmit Clock Check Control Register (XCLKCHK) Field Descriptions
  3872
- Transmitter DMA Event Control Register (XEVTCTL)
  3873
- Transmitter DMA Event Control Register (XEVTCTL) Field Descriptions
  3873
- Serializer Control Registers (Srctln)
  3874
- Serializer Control Registers (Srctln) Field Descriptions
  3874
- DIT Left Channel Status Registers (DITCSRA0-DITCSRA5)
  3875
- DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5)
  3875
- DIT Right Channel Status Registers (DITCSRB0-DITCSRB5)
  3875
- DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5)
  3875
- Receive Buffer Registers (Rbufn)
  3876
- Transmit Buffer Registers (Xbufn)
  3876
- Write FIFO Control Register (WFIFOCTL)
  3877
- Write FIFO Control Register (WFIFOCTL) Field Descriptions
  3877
- Write FIFO Status Register (WFIFOSTS)
  3878
- Write FIFO Status Register (WFIFOSTS) Field Descriptions
  3878
- Read FIFO Control Register (RFIFOCTL)
  3879
- Read FIFO Control Register (RFIFOCTL) Field Descriptions
  3879
- Mcasp Registers Accessed through Data Port
  3880
- Read FIFO Status Register (RFIFOSTS)
  3880
- Read FIFO Status Register (RFIFOSTS) Field Descriptions
  3880
- DCAN Connectivity Attributes
  3883
- DCAN Integration
  3883
- DCAN Clock Signals
  3884
- DCAN Pin List
  3884
- DCAN Block Diagram
  3885
- CAN Module General Initialization Flow
  3887
- CAN Bit-Timing Configuration
  3888
- CAN Core in Silent Mode
  3890
- CAN Core in Loopback Mode
  3891
- CAN Core in External Loopback Mode
  3892
- CAN Core in Loop Back Combined with Silent Mode
  3893
- CAN Interrupt Topology
  3895
- Local Power-Down Mode Flow Diagram
  3897
- Initialization of a Single Receive Object for Data Frames
  3900
- Initialization of a Transmit Object
  3900
- Initialization of a Single Receive Object for Remote Frames
  3901
- CPU Handling of a FIFO Buffer (Interrupt Driven)
  3906
- Bit Timing
  3907
- Parameters of the CAN Bit Time
  3908
- The Propagation Time Segment
  3908
- Synchronization on Late and Early Edges
  3910
- Filtering of Short Dominant Spikes
  3911
- Structure of the CAN Core's CAN Protocol Controller
  3912
- Data Transfer between IF1/IF2 Registers and Message RAM
  3916
- Field Descriptions
  3918
- Structure of a Message Object
  3918
- Message RAM Addressing in Debug/Suspend and RDA Mode
  3920
- Message RAM Representation in Debug/Suspend Mode
  3921
- Message RAM Representation in RAM Direct Access Mode
  3921
- Dcan Registers
  3922
- CTL Register
  3924
- CTL Register Field Descriptions
  3924
- Register Field Descriptions
  3927
- ERRC Register
  3929
- ERRC Register Field Descriptions
  3929
- BTR Register
  3930
- BTR Register Field Descriptions
  3930
- INT Register
  3931
- INT Register Field Descriptions
  3931
- TEST Register
  3932
- TEST Register Field Descriptions
  3932
- PERR Register
  3933
- PERR Register Field Descriptions
  3933
- ABOTR Register
  3934
- ABOTR Register Field Descriptions
  3934
- TXRQ_X Register
  3935
- TXRQ_X Register Field Descriptions
  3935
- TXRQ12 Register
  3936
- TXRQ12 Register Field Descriptions
  3936
- TXRQ34 Register
  3937
- TXRQ34 Register Field Descriptions
  3937
- TXRQ56 Register
  3938
- TXRQ56 Register Field Descriptions
  3938
- TXRQ78 Register
  3939
- TXRQ78 Register Field Descriptions
  3939
- NWDAT_X Register
  3940
- NWDAT_X Register Field Descriptions
  3940
- NWDAT12 Register
  3941
- NWDAT12 Register Field Descriptions
  3941
- NWDAT34 Register
  3942
- NWDAT34 Register Field Descriptions
  3942
- NWDAT56 Register
  3943
- NWDAT56 Register Field Descriptions
  3943
- NWDAT78 Register
  3944
- NWDAT78 Register Field Descriptions
  3944
- INTPND_X Register
  3945
- INTPND_X Register Field Descriptions
  3945
- INTPND12 Register
  3946
- INTPND12 Register Field Descriptions
  3946
- INTPND34 Register
  3947
- INTPND34 Register Field Descriptions
  3947
- INTPND56 Register
  3948
- INTPND56 Register Field Descriptions
  3948
- INTPND78 Register
  3949
- INTPND78 Register Field Descriptions
  3949
- MSGVAL_X Register
  3950
- MSGVAL_X Register Field Descriptions
  3950
- MSGVAL12 Register
  3951
- MSGVAL12 Register Field Descriptions
  3951
- MSGVAL34 Register
  3952
- MSGVAL34 Register Field Descriptions
  3952
- MSGVAL56 Register
  3953
- MSGVAL56 Register Field Descriptions
  3953
- MSGVAL78 Register
  3954
- MSGVAL78 Register Field Descriptions
  3954
- INTMUX12 Register
  3955
- INTMUX12 Register Field Descriptions
  3955
- INTMUX34 Register
  3956
- INTMUX34 Register Field Descriptions
  3956
- INTMUX56 Register
  3957
- INTMUX56 Register Field Descriptions
  3957
- INTMUX78 Register
  3958
- INTMUX78 Register Field Descriptions
  3958
- IF1CMD Register
  3959
- IF1CMD Register Field Descriptions
  3959
- IF1MSK Register
  3962
- IF1MSK Register Field Descriptions
  3962
- IF1ARB Register
  3963
- IF1ARB Register Field Descriptions
  3963
- IF1MCTL Register
  3964
- IF1MCTL Register Field Descriptions
  3964
- IF1DATA Register
  3966
- IF1DATA Register Field Descriptions
  3966
- IF1DATB Register
  3967
- IF1DATB Register Field Descriptions
  3967
- IF2CMD Register
  3968
- IF2CMD Register Field Descriptions
  3968
- IF2MSK Register
  3971
- IF2MSK Register Field Descriptions
  3971
- IF2ARB Register
  3972
- IF2ARB Register Field Descriptions
  3972
- IF2MCTL Register
  3973
- IF2MCTL Register Field Descriptions
  3973
- IF2DATA Register
  3975
- IF2DATA Register Field Descriptions
  3975
- IF2DATB Register
  3976
- IF2DATB Register Field Descriptions
  3976
- IF3OBS Register
  3977
- IF3OBS Register Field Descriptions
  3977
- IF3MSK Register
  3979
- IF3MSK Register Field Descriptions
  3979
- IF3ARB Register
  3980
- IF3ARB Register Field Descriptions
  3980
- IF3MCTL Register
  3981
- IF3MCTL Register Field Descriptions
  3981
- IF3DATA Register
  3983
- IF3DATA Register Field Descriptions
  3983
- IF3DATB Register
  3984
- IF3DATB Register Field Descriptions
  3984
- IF3UPD12 Register
  3985
- IF3UPD12 Register Field Descriptions
  3985
- IF3UPD34 Register
  3986
- IF3UPD34 Register Field Descriptions
  3986
- IF3UPD56 Register
  3987
- IF3UPD56 Register Field Descriptions
  3987
- IF3UPD78 Register
  3988
- IF3UPD78 Register Field Descriptions
  3988
- TIOC Register
  3989
- TIOC Register Field Descriptions
  3989
- RIOC Register
  3991
- RIOC Register Field Descriptions
  3991
- Unsupported Mcspi Features
  3994
- SPI Master Application
  3995
- SPI Slave Application
  3995
- Mcspi Clock Signals
  3996
- Mcspi Connectivity Attributes
  3996
- Mcspi Pin List
  3996
- SPI Full-Duplex Transmission
  3998
- SPI Half-Duplex Transmission (Receive-Only Slave)
  3999
- SPI Half-Duplex Transmission (Transmit-Only Slave)
  3999
- Phase and Polarity Combinations
  4001
- Full Duplex Single Transfer Format with PHA
  4002
- Full Duplex Single Transfer Format with PHA
  4003
- Continuous Transfers with SPIEN Maintained Active (Dual-Data-Pin Interface Mode)
  4008
- Continuous Transfers with SPIEN Maintained Active (Single-Data-Pin Interface Mode)
  4008
- Extended SPI Transfer with Start Bit PHA
  4010
- Chip Select ↔ Clock Edge Delay Depending on Configuration
  4011
- Chip-Select SPIEN Timing Controls
  4011
- CLKSPIO High/Low Time Computation
  4013
- Clock Granularity Examples
  4013
- FIFO Writes, Word Length Relationship
  4014
- Transmit/Receive Mode with no FIFO Used
  4015
- Transmit/Receive Mode with Only Receive FIFO Enabled
  4015
- Transmit/Receive Mode with both FIFO Direction Used
  4016
- Transmit/Receive Mode with Only Transmit FIFO Used
  4016
- Receive-Only Mode with FIFO Used
  4017
- Transmit-Only Mode with FIFO Used
  4017
- Buffer Almost Full Level (AFL)
  4018
- Buffer Almost Empty Level (AEL)
  4019
- Master Single Channel Initial Delay
  4020
- Example of SPI Slave with One Master and Multiple Slave Devices on Channel
  4023
- SPI Half-Duplex Transmission (Receive-Only Slave)
  4025
- SPI Half-Duplex Transmission (Transmit-Only Slave)
  4026
- SPI Registers
  4032
- Mcspi Revision Register (MCSPI_REVISION)
  4034
- Mcspi System Configuration Register (MCSPI_SYSCONFIG)
  4035
- Mcspi System Status Register (MCSPI_SYSSTATUS)
  4036
- Mcspi Interrupt Status Register (MCSPI_IRQSTATUS)
  4037
- Mcspi Interrupt Status Register (MCSPI_IRQSTATUS) Field Descriptions
  4038
- Mcspi Interrupt Enable Register (MCSPI_IRQENABLE)
  4040
- Mcspi Interrupt Enable Register (MCSPI_IRQENABLE) Field Descriptions
  4041
- Mcspi System Register (MCSPI_SYST)
  4042
- Mcspi System Register (MCSPI_SYST) Field Descriptions
  4043
- Mcspi Module Control Register (MCSPI_MODULCTRL)
  4044
- Mcspi Module Control Register(MCSPI_MODULCTRL) Field Descriptions
  4045
- Mcspi Channel (I) Configuration Register (MCSPI_CH(I)Conf) Field Descriptions
  4046
- Data Lines Configurations
  4049
- Mcspi Channel (I) Status Register (MCSPI_CH(I)Stat)
  4050
- Mcspi Channel (I) Control Register (MCSPI_CH(I)CTRL)
  4051
- Mcspi Channel (I) Receive Register (MCSPI_RX(I))
  4052
- Mcspi Channel (I) Transmit Register (MCSPI_TX(I))
  4052
- Mcspi Transfer Levels Register (MCSPI_XFERLEVEL)
  4053
- GPIO0 Module Integration
  4058
- GPIO[1-3] Module Integration
  4058
- GPIO Clock Signals
  4059
- GPIO0 Connectivity Attributes
  4059
- GPIO[1:3] Connectivity Attributes
  4059
- GPIO Pin List
  4060
- Interrupt Request Generation
  4063
- Write @ GPIO_CLEARDATAOUT Register Example
  4065
- Write @ Gpio_Setirqenablex Register Example
  4066
- General-Purpose Interface Used as a Keyboard Interface
  4067
- Gpio Registers
  4068
- GPIO_REVISION Register
  4069
- GPIO_REVISION Register Field Descriptions
  4069
- GPIO_SYSCONFIG Register
  4070
- GPIO_SYSCONFIG Register Field Descriptions
  4070
- GPIO_EOI Register
  4071
- GPIO_IRQSTATUS_RAW_0 Register
  4072
- GPIO_IRQSTATUS_RAW_1 Register
  4073
- GPIO_IRQSTATUS_0 Register
  4074
- GPIO_IRQSTATUS_1 Register
  4075
- GPIO_IRQSTATUS_SET_0 Register
  4076
- GPIO_IRQSTATUS_SET_1 Register
  4077
- GPIO_IRQSTATUS_CLR_0 Register
  4078
- GPIO_IRQSTATUS_CLR_1 Register
  4079
- GPIO_IRQWAKEN_0 Register
  4080
- GPIO_IRQWAKEN_0 Register Field Descriptions
  4080
- GPIO_IRQWAKEN_1 Register
  4081
- GPIO_IRQWAKEN_1 Register Field Descriptions
  4081
- GPIO_SYSSTATUS Register
  4082
- GPIO_SYSSTATUS Register Field Descriptions
  4082
- GPIO_CTRL Register
  4083
- GPIO_CTRL Register Field Descriptions
  4083
- GPIO_OE Register
  4084
- GPIO_DATAIN Register
  4085
- GPIO_DATAIN Register Field Descriptions
  4085
- GPIO_DATAOUT Register
  4086
- GPIO_DATAOUT Register Field Descriptions
  4086
- GPIO_LEVELDETECT0 Register
  4087
- GPIO_LEVELDETECT0 Register Field Descriptions
  4087
- GPIO_LEVELDETECT1 Register
  4088
- GPIO_LEVELDETECT1 Register Field Descriptions
  4088
- GPIO_RISINGDETECT Register
  4089
- GPIO_RISINGDETECT Register Field Descriptions
  4089
- GPIO_FALLINGDETECT Register
  4090
- GPIO_FALLINGDETECT Register Field Descriptions
  4090
- GPIO_DEBOUNCENABLE Register
  4091
- GPIO_DEBOUNCENABLE Register Field Descriptions
  4091
- GPIO_DEBOUNCINGTIME Register
  4092
- GPIO_DEBOUNCINGTIME Register Field Descriptions
  4092
- GPIO_CLEARDATAOUT Register
  4093
- GPIO_CLEARDATAOUT Register Field Descriptions
  4093
- GPIO_SETDATAOUT Register
  4094
- GPIO_SETDATAOUT Register Field Descriptions
  4094
- Public ROM Code Architecture
  4096
- Public ROM Code Boot Procedure
  4097
- ROM Memory Map
  4098
- Dead Loops
  4099
- ROM Exception Vectors
  4099
- Public RAM Memory Map
  4100
- RAM Exception Vectors
  4100
- Tracing Data
  4101
- Crystal Frequencies Supported
  4102
- ROM Code Startup Sequence
  4102
- ROM Code Booting Procedure
  4103
- ROM Code Default Clock Settings
  4103
- 26.1.5.2.1 SYSBOOT Configuration Pins
  4105
- Fast External Boot
  4113
- Memory Booting
  4114
- GPMC XIP Timings
  4116
- XIP Timings Parameters
  4116
- Pins Used for Muxed nor Boot
  4117
- Pins Used for Non-Muxed nor Boot
  4117
- Image Shadowing on GP Device
  4118
- Special SYSBOOT Pins for nor Boot
  4118
- GPMC NAND Timings
  4119
- NAND Timings Parameters
  4119
- ONFI Parameters
  4120
- Supported NAND Devices
  4120
- 4Th NAND ID Data Byte
  4122
- NAND Geometry Information on I2C EEPROM
  4122
- Pins Used for NANDI2C Boot for I2C EEPROM Access
  4122
- ECC Configuration for NAND Boot
  4123
- NAND Device Detection
  4124
- NAND Invalid Blocks Detection
  4125
- NAND Read Sector Procedure
  4126
- ECC Data Mapping for 2 KB Page and 8B BCH Encoding
  4127
- ECC Data Mapping for 4 KB Page and 16B BCH Encoding
  4128
- Pins Used for NAND Boot
  4128
- MMC/SD Booting
  4130
- MMC/SD Detection Procedure
  4131
- Configuration Header Settings
  4132
- Configuration Header TOC Item
  4132
- Master Boot Record Structure
  4134
- MMC/SD Booting, Get Booting File
  4134
- MBR Detection Procedure
  4135
- Partition Entry
  4135
- Partition Types
  4135
- FAT Boot Sector
  4136
- MBR, Get Partition
  4136
- FAT Detection Procedure
  4139
- FAT Directory Entry
  4140
- FAT Entry Description
  4141
- Pins Used for MMC0 Boot
  4141
- Pins Used for MMC1 Boot
  4141
- Pins Used for SPI Boot
  4142
- Blocks and Sectors Searched on Non-XIP Memories
  4143
- Peripheral Booting Procedure
  4143
- Pins Used for EMAC Boot in MII Mode
  4146
- Pins Used for EMAC Boot in RGMII Mode
  4146
- Pins Used for EMAC Boot in RMII Mode
  4146
- Ethernet PHY Mode Selection
  4147
- Pins Used for UART Boot
  4147
- Customized Descriptor Parameters
  4148
- USB Initialization Procedure
  4148
- Image Transfer for USB Boot
  4149
- Pins Used for USB Boot
  4149
- GP Device Image Format
  4150
- Image Formats on GP Devices
  4150
- Booting Parameters Structure
  4151
- Tracing Vectors
  4153
- Wakeup Booting by ROM
  4153
- Debug Subsystem Registers
  4157
- Suspend Control Registers
  4158
- Suspend Control Registers Field Descriptions
  4158
- Document Revision History
  4159

Texas Instruments AM335 Series Design Manual (39 pages)

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