General Timing Rules - ST STM32F205 series Reference Manual

Flexible static memory controller (FSMC)
Table 178. NOR Flash/PSRAM controller: example of supported memories and transactions
Device
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
PSRAM
Asynchronous
(multiplexed and
nonmultiplexed
Asynchronous page
I/Os)
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
SRAM and ROM
Asynchronous
Asynchronous
31.5.3

General timing rules

Signals synchronization
•
All controller output signals change on the rising edge of the internal clock (HCLK)
• In synchronous mode (read or write), all output signals change on the rising edge of
HCLK. Whatever the CLKDIV value, all outputs change as follows:
–
–
1268/1378
Mode R/W
R
W
R
W
R
W
R
R
R
R
W
W
R
W
R
W
NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the
falling edge of FSMC_CLK clock.
NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising
edge of FSMC_CLK clock.
AHB Allowed/
Memory
data
data size
size allowed
8 16
8 16
16 16
16 16
32 16
32 16
- 16
8 16
16 16
32 16
8 16
16 / 32 16
8 / 16 16
8 / 16 16
32 16
32 16
RM0033 Rev 8
not Comments
Y -
Y Use of byte lanes NBL[1:0]
Y -
Y -
Y Split into two FSMC accesses
Y Split into two FSMC accesses
N Mode is not supported
N -
Y -
Y -
Y Use of byte lanes NBL[1:0]
Y -
Y -
Y Use of byte lanes NBL[1:0]
Y Split into two FSMC accesses
Split into two FSMC accesses.
Y
Use of byte lanes NBL[1:0]
RM0033