Hsi Clock; Pll Configuration; Lse Clock - ST STM32F410 Reference Manual

RM0401
5.2.2

HSI clock

The HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used
directly as a system clock, or used as PLL input.
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster startup time than the HSE crystal oscillator however, even
with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at T
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the
control register
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the
The HSIRDY flag in the
stable or not. At startup, the HSI RC output clock is not released until this bit is set by
hardware.
The HSI RC can be switched on and off using the HSION bit in the
register (RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to
5.2.3

PLL configuration

The STM32F410 devices feature one PLL. The PLL (PLL) is clocked by the HSE or HSI
oscillator and features three different output clocks:
•
The first output is used to generate the high speed system clock (up to 100 MHz)
•
The second output is used to generate the RNG clock.
•
The third output is used to generate an accurate clock to achieve high-quality audio
performance on the I2S interface.
Since the PLL configuration parameters cannot be changed once the PLL is enabled, it is
recommended to configure the PLL before enabling it (selection of the HSI or HSE oscillator
as PLL clock source, and configuration of division factors M, P, Q, R and multiplication factor
N).
The PLL is disabled by hardware when entering Stop and Standby modes, or when an HSE
failure occurs when HSE or PLL (clocked by HSE) are used as system clock. The PLL can
be configured through
5.2.4

LSE clock

The LSE clock is generated using a 32.768kHz low speed external crystal or ceramic
resonator. It has the advantage providing a low-power but highly accurate clock source to
the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
(RCC_CR).
RCC clock control register
RCC clock control register (RCC_CR)
Section 5.2.7: Clock security system (CSS) on page
RCC PLL configuration register
(RCC_CR).
RM0401 Rev 3
Reset and clock control (RCC)
indicates if the HSI RC is
RCC clock control
(RCC_PLLCFGR).
= 25 °C.
A
RCC clock
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