Pll Configuration; Lse Clock - ST STM32F207 Series Reference Manual

Reset and clock control (RCC)
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at T
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the
control register
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the
The HSIRDY flag in the
stable or not. At startup, the HSI RC output clock is not released until this bit is set by
hardware.
The HSI RC can be switched on and off using the HSION bit in the
register (RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to
5.2.3

PLL configuration

The STM32F2xx devices feature two PLLs:
•
A main PLL (PLL) clocked by the HSE or HSI oscillator and featuring two different
output clocks:
–
–
• A dedicated PLL (PLLI2S) used to generate an accurate clock to achieve high-quality
audio performance on the I2S interface.
Since the main-PLL configuration parameters cannot be changed once PLL is enabled, it is
recommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as
PLL clock source, and configuration of division factors M, N, P, and Q).
The PLLI2S uses the same input clock as PLL (PLLM[5:0] and PLLSRC bits are common to
both PLLs). However, the PLLI2S has dedicated enable/disable and division factors (N and
R) configuration bits. Once the PLLI2S is enabled, the configuration parameters cannot be
changed.
The two PLLs are disabled by hardware when entering Stop and Standby modes, or when
an HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock.
PLL configuration register (RCC_PLLCFGR)
(RCC_CFGR)
5.2.4

LSE clock

The LSE crystal is a 32.768 kHz low-speed external (LSE) crystal or ceramic resonator. It
has the advantage providing a low-power but highly accurate clock source to the real-time
clock peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in
register (RCC_BDCR).
90/1381
(RCC_CR).
RCC clock control register
RCC clock control register (RCC_CR)
Section 5.2.7: Clock security system (CSS) on page
The first output is used to generate the high speed system clock (up to 120 MHz)
The second output is used to generate the clock for the USB OTG FS (48 MHz),
the random analog generator (≤48 MHz) and the SDIO (≤ 48 MHz).
can be used to configure PLL and PLLI2S, respectively.
(RCC_CR).
and RCC clock configuration register
RM0033 Rev 9
RM0033
= 25 °C.
A
RCC clock
indicates if the HSI RC is
RCC clock control
91.
RCC Backup domain control
RCC