Timer Output Master Enable Register (Toer) - Hitachi H8/3032 Series Hardware Manual

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Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or
whether GRB3 is buffered by BRB3.
Bit 1
BFB3 Description
0 GRB3 operates normally
1 GRB3 is buffered by BRB3
Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or
whether GRA3 is buffered by BRA3.
Bit 0
BFA3 Description
0 GRA3 operates normally
1 GRA3 is buffered by BRA3

8.2.5 Timer Output Master Enable Register (TOER)

TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3
and 4.
Bit 7
—
Initial value 1
Read/Write —
Reserved bits
TOER is initialized to H'FF by a reset and in standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 1.
6 5 4 3
— EXB4 EXA4 EB3
1 1 1 1
— R/W R/W R/W
Master enable TOCXA , TOCXB
4
These bits enable or disable output
settings for pins TOCXA4 and TOCXB4
Master enable TIOCA
These bits enable or disable output settings for pins
TIOCA3, TIOCB3 , TIOCA4, and TIOCB4
189
(Initial value)
(Initial value)
2 1 0
EB4 EA4 EA3
1 1 1
R/W R/W R/W
4
, TIOCB , TIOCA , TIOCB
3 3 4 4