Fpga Tx Interface; Functional Description; Interface Width Configuration - Xilinx Virtex-6 FPGA User Manual

Chapter 3: Transmitter
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FPGA TX Interface

Functional Description

The FPGA TX interface is the FPGA's gateway to the TX datapath of the GTX transceiver.
Applications transmit data through the GTX transceiver by writing data to the TXDATA
port on the positive edge of TXUSRCLK2. The width of the port can be configured to be
one, two, or four bytes wide. The actual width of the port depends on the
TX_DATA_WIDTH attribute and TXENC8B10BUSE port settings. Port widths can be 8, 10,
16, 20, 32, and 40 bits.
The rate of the parallel clock (TXUSRCLK2) at the interface is determined by the TX line
rate, the width of the TXDATA port, and whether or not 8B/10B encoding is enabled. In
some operating modes, a second parallel clock (TXUSRCLK) must be provided for the
internal PCS logic in the transmitter. This section shows how to drive the parallel clocks
and explains the constraints on those clocks for correct operation. The highest transmitter
data rates require a 4-byte interface to achieve a TXUSRCLK2 rate in the specified
operating range.

Interface Width Configuration

The Virtex®-6 FPGA GTX transceiver contains an internal 2-byte datapath. The FPGA
interface width is configurable by setting the TX_DATA_WIDTH attribute. When the
8B/10B encoder is enabled, the FPGA interface must be configured to 10 bits, 20 bits, or
40 bits. When the 8B/10B encoder is bypassed, the FPGA interface is configured to any of
the available widths: 8, 10, 16, 20, 32, or 40 bits.
the TX datapath is selected. 8B/10B encoding is described in more detail in
Encoder, page
Table 3-1: FPGA TX Interface Datapath Configuration
TXENC8B10BUSE
1
0
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128
TX Oversampling, page 166
TX Polarity Control, page 166
TX Fabric Clock Output Control, page 167
TX Configurable Driver, page 172
TX Receiver Detect Support for PCI Express Designs, page 179
TX Out-of-Band Signaling, page 180
143.
TX_DATA_WIDTH
10
20
40
8
10
16
20
32
40
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Table 3-1 shows how the interface width for
FPGA Interface Width
8 bits
16 bits
32 bits
8 bits
10 bits
16 bits
20 bits
32 bits
40 bits
Virtex-6 FPGA GTX Transceivers User Guide
TX 8B/10B
Internal Data Width
20 bits
20 bits
20 bits
16 bits
20 bits
16 bits
20 bits
16 bits
20 bits
UG366 (v2.5) January 17, 2011