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Xilinx Virtex-4 RocketIO User Manual

Xilinx Virtex-4 RocketIO User Manual

Multi-gigabit transceiver
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Virtex-4 RocketIO
Multi-Gigabit
Transceiver
User Guide
UG076 (v4.1) November 2, 2008
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Summary of Contents for Xilinx Virtex-4 RocketIO

  • Page 1 Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide UG076 (v4.1) November 2, 2008...
  • Page 2 Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.

  • Page 3: Revision History

    MGTs. Existing material edited and updated. • Added new section “SelectIO-to-MGT Crosstalk”to Chapter 6, “Analog and Board Design Considerations.” • Added Appendix D, “Special Analog Functions.” Previously part of Chapter UG076 (v4.1) November 2, 2008 www.xilinx.com Virtex-4 RocketIO MGT User Guide...
  • Page 4 • Modified text in “8B/10B Encoding/Decoding.” • Modified text in paragraph before Figure 3-4. • Removed 64B/66B from Table 3-4. • Removed PCS_BIT_SLIP from “Symbol Alignment and Detection (Comma Detection).” Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 5 “Optimal Cable Length.” Appendix • Removed 64B/66B from and modified descriptions of TXOUTCLK1/2 and RXRECCLK1/2 in Table A-1. • Added notes to Figure A-1, Table A-6, and Table A-7. UG076 (v4.1) November 2, 2008 www.xilinx.com Virtex-4 RocketIO MGT User Guide...
  • Page 6 • Removed discrete equalization row from Table E-10. Modified references in Appendix 11/02/08 Added a new paragraph regarding 2.5V power and filtering to “Powering Unused MGTs” in Chapter Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 7: Table Of Contents

    ..........77 Virtex-4 RocketIO MGT User Guide www.xilinx.com...
  • Page 8 ..........122 ALIGN_COMMA_WORD www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 9 64-Bit Example ............158 Virtex-4 RocketIO MGT User Guide www.xilinx.com...
  • Page 10 Receiver ..............192 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 11 Usage ..............228 Virtex-4 RocketIO MGT User Guide www.xilinx.com...
  • Page 12 ............250 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 13 ........321 Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO...
  • Page 14 Pre-emphasis, Differential Swing, and Equalization ......331 Appendix F: References www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 15 Figure 3-1: Transmit Architecture ..........101 Virtex-4 RocketIO MGT User Guide www.xilinx.com...
  • Page 16 Figure 5-6: CRC Generation Diagram ......... . 161 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 17 Figure 8-19: RX Low Latency Buffer Bypass Mode: Use Model RX_2A ... . . 225 Figure 8-20: RX Low Latency Buffer Bypass Mode: Use Model RX_2B ... . . 226 Virtex-4 RocketIO MGT User Guide www.xilinx.com...
  • Page 18 Figure 12-2: BGA Escape Design Example ........261 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 19 Appendix C: Dynamic Reconfiguration Port Appendix D: Special Analog Functions Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO Transceiver Design Migration Figure E-1: Reference Clock Selection for Each Device ......326 Figure E-2: Virtex-II, Virtex-II Pro, and Virtex-4 Power Supply Filtering .
  • Page 20 Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 21 Table 3-6: 8B/10B Bypassed Signal Significance ....... . . 113 Virtex-4 RocketIO MGT User Guide www.xilinx.com...
  • Page 22 Table 6-3: SelectIO Pin Guidance for XC4VFX60/40/20-FF672..... . 175 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 23 Table 8-17: Latency for Use Model RX_2A ........232 Virtex-4 RocketIO MGT User Guide www.xilinx.com...
  • Page 24 Table C-9: Dynamic Reconfiguration Port Memory Map: MGTA Address 63–67..301 Table C-10: Dynamic Reconfiguration Port Memory Map: MGTA Address 68–6C . . . 302 Table C-11: Dynamic Reconfiguration Port Memory Map: MGTA Address 6D–71 . . . 303 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 25 Table D-1: Register Address Location ......... . 321 Table D-2: Example RXSELDACTRAN and RXSELDACFIX Combinations ..321 Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO Transceiver Design Migration Table E-1: MGTs per Device.
  • Page 26 Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 27: Preface: About This Guide

    Flexible Cyclic Redundancy Check (CRC) generation and checking • Pins for transmitter and receiver termination voltage • User reconfiguration using the Dynamic Reconfiguration Port • Multiple loopback paths • NRZ signaling Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 28: User Guide Organization

    Appendix D, “Special Analog Functions” – Receiver Sample Phase Adjustment function. • Appendix E, “Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO Transceiver Design Migration” – Important differences to be aware of when migrating designs from Virtex-II Pro/ Virtex-II Pro X to Virtex-4 FPGAs.

  • Page 29: Related Information

    Related Information Related Information For a complete menu of online information resources available on the Xilinx website, visit http://www.xilinx.com/virtex4/. For a comprehensive listing of available tutorials and resources on network technologies and communications protocols, visit http://www.iol.unh.edu/training/. Additional Resources For additional information, go to http://support.xilinx.com. The following table lists some of the resources available on this website.

  • Page 30: Port And Attribute Names

    RJ is additive as the sum of squares and follows a normal distribution. MGT Definition The term MGT refers to the Virtex-4 RocketIO Multi-Gigabit Transceiver. Previous generations are explicitly called out: Virtex-II Pro RocketIO or Virtex-II Pro X RocketIO X.

  • Page 31: Typographical

    Separates items in a list of Vertical bar | lowpwr ={on|off} choices Repetitive material that has allow block block_name Ellipsis . . . been omitted loc1 loc2 ... locn; Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 32 Preface: About This Guide www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 33: Section I

    Section I: FPGA Level Design Virtex-4 RocketIO Multi-Gigabit Transceiver...
  • Page 34 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 35: Basic Architecture And Capabilities

    10 Gigabit Fibre Channel (4 x 3.1875G) 3.1875 Aurora Protocol 1/2/3/4... 0.622 – 6.5 Notes: 1. One channel is considered to be one transceiver. 2. See www.xilinx.com/aurora for details. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 36: Figure 1-1: Rocketio Multi-Gigabit Transceiver Block Diagram

    Notes: (1) 64B/66B encoding/decoding is not supported. (2) TXPCSHCLKOUT and RXPCSHCLKOUT ports are not supported. (3) RXCALFAIL, RXCYCLELIMIT, TXCALFAIL, and TXCYCLELIMIT ports are not supported. ug076_apA_01_071707 Figure 1-1: RocketIO Multi-Gigabit Transceiver Block Diagram www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 37 250.0 125.00 37.50 Serial ATA Type 2 8B/10B 300.0 75.00 75.00 Serial ATA Type 1 8B/10B 300.0 150.00 125.00 PCI Express 8B/10B 250.0 250.00 125.00 Infiniband 8B/10B 250.0 250.00 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 38 3. Parallel data frequency is limited by the maximum USRCLK2 frequency of 250 MHz. 4. Receiver in digital CDR mode. 5. These protocols also allow a 125.0 MHz reference clock. A higher reference clock frequency yields lower wide-band jitter generation. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 39: Configuring The Rocketio Mgt

    MGT configuration can be complex because of the large number of possible settings. There are over 200 ports and attributes available, and many of them are interrelated. Xilinx provides a RocketIO wizard to help manage the configuration process. The wizard is highly recommended for any RocketIO design.
  • Page 40 CRC value. TXCRCPD Powers down the TX CRC logic when set to logic 1. TXCRCRESET Resets the TX CRC logic when set to a logic 1. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 41 “Simulation and Implementation,” for package pin correlation to MGT location constraint. Differential serial output (external package pin). See Chapter 7, “Simulation and Implementation,” for package pin correlation to MGT location constraint. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 42 TX VCO TXPMARESET calibration is controlled by TXPMARESET. See “Resets” in Chapter RXPCSHCLKOUT Reserved. This clock port is not supported. TXPCSHCLKOUT Reserved. This clock port is not supported. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 43 Reserved. Tie to logic 0. RXIGNOREBTF Reserved. Tie to logic 0. RXLOSSOFSYNC Reserved. TXENC64B66BUSE Reserved. Tie to logic 0. TXGEARBOX64B66BUSE Reserved. Tie to logic 0. TXSCRAM64B66BUSE Reserved. Tie to logic 0. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 44 TXDATA bus section (see Figure 3-10, page 111) for each byte specified by the byte-mapping section. The bits have no meaning if TXENC8B10BUSE is set to a logic 0. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 45 Sets the internal mode of the receive PCS: RXINTDATAWIDTH 2’b10 = 32-bit 2’b11 = 40-bit Transmit data from the FPGA user fabric that is 8 bytes wide. TXDATA TXDATA[7:0] is always the first byte transmitted. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 46 Clock input that clocks the transmit data and status between TXUSRCLK2 the FPGA core and the transceiver. Typically the same as RXUSRCLK2. Notes: 1. 64B/66B encoding/decoding is not supported. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 47 PLLs. Connects to the COMBUSOUT of the other GT11 in the tile to COMBUSIN allow proper simulation of shared clocks and PLLs. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 48: Attributes

    TRUE/FALSE, the TRUE state is the default. Note: Xilinx recommends using the RocketIO wizard to set attributes. The wizard manages dependencies between parameters and applies design-rule checks to prevent invalid configurations. Table 1-10: RocketIO MGT CRC Attributes...
  • Page 49 TRUE: CRC clock inverted. During normal operation, this should always be set to FALSE. Notes: 1. RapidIO uses a 16-bit CRC, which cannot be generated or checked using the MGT’s CRC-32 block. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 50 Reserved. This feature is not supported. Use the RocketIO Wizard to RXEQ set this attribute. 5-bit Transmitter data amplitude control. See “Output Swing and TXDAT_TAP_DAC Binary Emphasis” in Chapter www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 51 Chapter 2, “Clocking, Timing, and Resets” for more details. FALSE/TRUE. FALSE: RXRECCLK1 = synchronous PCS RXCLK RXRECCLK1_USE_SYNC Boolean TRUE: RXRECCLK1 = asynchronous PCS RXCLK Chapter 2, “Clocking, Timing, and Resets” for more details. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 52 FALSE: Powers down RXA, RXB, and TXAB FALSE/TRUE. FALSE: Performs PCS clock phase alignment when RXSYNC is PMA_BIT_SLIP Boolean set to logic 1. TRUE: PCS clock phase alignment is disabled. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 53 Reserved. Use the RocketIO wizard to set this attribute. Binary TRUE/FALSE. TRUE: Powers up the PCS and Digital Receiver of the transceiver. POWER_ENABLE Boolean FALSE: Powers down the PCS and Digital Receiver of the transceiver. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 54 These define the channel bonding sequence. The usage of these vectors also depends on CHAN_BOND_SEQ_LEN and 11-bit CHAN_BOND_SEQ_2_USE. For details, see section entitled CHAN_BOND_SEQ_1_1, 2, 3, 4 Binary “CHAN_BOND_SEQ_1_MASK, CHAN_BOND_SEQ_2_MASK, CHAN_BOND_SEQ_LEN, CHAN_BOND_SEQ_*_* Attributes” in Chapter www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 55 These define the sequence for clock correction. The attribute used depends on the CLK_COR_SEQ_LEN and CLK_COR_SEQ_2_USE. 11-bit CLK_COR_SEQ_1_1, 2, 3, 4 For details, see section “CLK_COR_SEQ_1_MASK, Binary CLK_COR_SEQ_2_MASK, CLK_COR_SEQ_LEN Attributes” in Chapter Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 56 PCOMMA_32B_VALUE and MCOMMA_32B_VALUE. TRUE/FALSE. TRUE: RXCOMMADET is raised when the data aligner matches MCOMMA_DETECT Boolean on MCOMMA_32B_VALUE. FALSE: RXCOMMADET does not respond to MCOMMA_32B_VALUE matches. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 57 (if DEC_MCOMMA_DETECT is TRUE) 64B/66B SH_CNT_MAX Integer Reserved. Use the RocketIO Wizard to set this attribute. SH_INVALID_CNT_MAX Integer Reserved. Use the RocketIO Wizard to set this attribute. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 58 TRUE: RX ring buffer is used FALSE: RX ring buffer is bypassed TRUE/FALSE. Controls bypassing the TX buffer. TX_BUFFER_USE Boolean TRUE: TX buffer is used FALSE: TX buffer is bypassed www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 59 FALSE: Enable receiver deserializer. TRUE: Reset receiver deserializer. Notes: 1. Buffer bypass mode used in conjunction with the digital receiver is not supported. DIGRX_SYNC_MODE must always be set to FALSE. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 60: Byte Mapping

    FPGA fabric interface on the same clock cycle. Table 1-15: Control/Status Bus Association to Data Bus Byte Paths Control/Status Bit Data Bits [7:0] [15:8] [23:16] [31:24] [39:32] [47:40] [55:48] [63:56] www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 61: Chapter 2: Clocking, Timing, And Resets

    This is because a single PLL is shared by the transmitters, whereas each receiver has an independent PLL and CDR. In a Virtex-4 device, there are eleven clock inputs into each Virtex-4 RocketIO MGT instantiation. There are three reference inputs to choose from: •...

  • Page 62: Figure 2-1: Mgt Column Clocking

    PMA RXCLK B Receive PLL B Dividers MGTCLK REFCLK RXBPMACLKSEL Reference Clock Routing PMA RXBCLK Note: (1) The PMA RXBCLK clock path is not supported. ug076_ch2_01_071807 Figure 2-1: MGT Column Clocking www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 63: Gt11Clk_Mgt And Reference Clock Routing

    This input is connected to SYNCLK2OUT of an adjacent SYNCLK2IN GT11CLK or GT11CLK_MGT. Attributes Determines which clock input is used for the reference clock REFCLKSEL (MGTCLK, RXBCLK, REFCLK, SYNCLK1IN, SYNCLK2IN). Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 64: Mgt Clock Ports And Attributes

    Reserved. This clock port is not supported. CRC Clocks RXCRCCLK Clocks the internal receiver CRC logic. RXCRCINTCLK Clocks the CRC/FPGA fabric interface. TXCRCCLK Clocks the internal transmitter CRC logic. TXCRCINTCLK Clocks the CRC/FPGA fabric interface. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 65 This implementation using the MGT’s RXMCLK output and the GT11CLK module’s RXBCLK input is shown in Figure 2-1, page 62. This is an unsupported test feature and is not recommended for normal operating modes. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 66: Common Reference Clock Use Models

    SYNCLK1OUTEN = ENABLE SYNCLK2OUTEN = DISABLE GT11_inst2 REFCLK1 REFCLK2 GT11_inst3 GT11CLK_MGT_inst2 REFCLK1 MGTCLK_P REFCLK2 MGTCLK_N SYNCLK1OUTEN = DISABLE SYNCLK2OUTEN = ENABLE UG076_CH2_04_021805 Figure 2-2: High-Speed Dedicated Clocks (GT11CLK_MGT Instance) www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 67: Fabric Clocks

    SYNCLK2OUTEN = ENABLE drives the entire column fabric clocking resources. REFCLKSEL = REFCLK via the SYNCLK clock trees. UG076_CH2_06_050806 Figure 2-3: REFCLK and GREFCLK Options for an MGT Tile Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 68: Pma Transmit Clocks

    4. This path must be used if TXOUTCLK1 is used to generate the PCS user clocks for low-latency applications requiring bypass of the PCS TXBUFFER. Refer to Chapter 8 for details. 5. TXOUTCLK1 is a fabric port. 6. TXPCSHCLKOUT port is not supported. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 69 1. For lower wide-band jitter generation, choose a reference clock frequency that uses a lower feedback divider. 2. Line Rate = VCO Frequency*2/TXOUTDIV2SEL. 3. Reference Clock = VCO Frequency/TXPLLNDIVSEL Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 70: Pma Receive Clocks

    PCS RXBUFFER. Refer to Chapter 8 for details. 5. RXRECCLK1 is a fabric port. 6. RXPCSHCLKOUT port is not supported. 7. RXMCLK port is not supported. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 71 01= 2XCLK (2-byte clock) 10, 11 10= 4XCLK (1-byte clock) FALSE: RXRECCLK1 = synchronous PCS RXCLK RXRECCLK1_USE_SYNC FALSE/TRUE TRUE: RXRECCLK1 = asynchronous PCS RXCLK Notes: 1. See Figure 2-11 for application-specific settings. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 72: Rx And Tx Pll Voltage-Controlled Oscillator (Vco) Operating Frequency

    2.15 Gb/s–2.48 Gb/s, and 4.3 Gb/s–4.96 Gb/s is not supported. Figure 2-6 illustrates the supported data rates for the Transmitter (Tx), the Receiver in Digital CDR Mode (Rx DCDR), and the Receiver in Analog CDR Mode (Rx ACDR). www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 73: Figure 2-6: Transmitter And Receiver Line Rates

    Clock Distribution DCDR ACDR ACDR ACDR UG076_ch2_27_061407 Figure 2-6: Transmitter and Receiver Line Rates Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 74: Pma/Pcs Clocking Domains And Data Paths

    RXRECCLK1/ Clock RXRECCLK2 Control ENMCOMMAALIGN RXBLOCKSYNC64B66BUSE, RXDEC8B10BUSE, RX_BUFFER_USE RXDEC64B66BUSE, ENPCOMMAALIGN RXCOMMADETUSE RXDESCRAM64B66BUSE RXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_01_061507 Figure 2-7: PCS Receive Clocking Domains and Datapaths www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 75: Pma Configurations

    There are several configurations of the PMA that also affect serial speeds and clocking schemes. These configurations can be modified by the Dynamic Reconfiguration Port or with attributes. These settings are covered in Figure 2-11 Figure 2-12. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 76: Figure 2-9: Low-Latency Clocking

    MGT. Notes: 1. BUFG connect is possible with TXOUTCLK1 or RXRECCLK1 with the use of fabric interconnect. ug076_ch2_10_061507 Figure 2-9: Low-Latency Clocking www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 77: Setting The Clocking Options

    The reference clock can directly drive the USRCLKs. Because most cases require multiple frequencies to clock data, it is recommended to use TXOUTCLK1 and RXRECCLK1 in conjunction with the internal clock dividers. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 78: Figure 2-11: Receive Clocking Decision Flow (Page 1 Of 2)

    7. Channel Bonding requires that the USRCLK is provided via the fabric. 8. 64B/66B encoding/decoding is not supported. ug076_ch2_08a_071807 Figure 2-11: Receive Clocking Decision Flow (Page 1 of 2) www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 79: Figure 2-11 (Cont'd): Receive Clocking Decision Flow (Page 2 Of 2)

    = 11 TRUE? DIGRX_SYNC_MODE = 0 DIGRX_SYNC_MODE = 1 DONE with Settings RXCLK0_FORCE_PMACLK = FALSE RXCLK0_FORCE_PMACLK = TRUE ug076_ch2_08b_072607 Figure 2-11 (Cont’d): Receive Clocking Decision Flow (Page 2 of 2) Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 80: Figure 2-12: Transmit Clocking Decision Flow (Page 1 Of 2)

    Use SONET or no 64B/66B? encoding TXCLKMODE[3:0] TXCLKMODE[3:0] TXCLKMODE[3:0] = 1110 = 0100 = 1001 ug076_ch2_09a_061507 (cont'd on next page) Figure 2-12: Transmit Clocking Decision Flow (Page 1 of 2) www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 81: Figure 2-12 (Cont'd): Transmit Clocking Decision Flow (Page 2 Of 2)

    TX _ CLOCK _ DIVIDER = 00 = 10 = 01 = 11 DONE with TX settings ug076_ch2_09b_072607 Figure 2-12 (Cont’d): Transmit Clocking Decision Flow (Page 2 of 2) Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 82: Special Clocking Considerations

    LOCKED CLKIN REFCLK 1 REFCLK 1 GT11 GT11 RXCLKSTABLE RXCLKSTABLE TXCLKSTABLE TXCLKSTABLE Virtex-4 FX Device RXRECCLK1/ RXRECCLK2 GT11 REFCLK 1 ug076_ch2_14_050806 Figure 2-13: External PLL Locked Signal for MGT www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 83: Resets

    0, but its frequency is incorrect because the PLL is not locked. Following is a list of requirements for RXPMARESET: Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 84: Txreset

    RXRESET must be deasserted synchronously on all channel-bonded MGTs with respect to RXUSRCLK2. The blocks affected by RXRESET are: • RX Fabric Interface — RXUSRCLK and RXUSRCLK2 domains • 8B/10B Decode — RXUSRCLK domain www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 85: Crc Reset

    !system_reset && (RXLOCK == 1 for 16K [16 x 1024] REFCLK cycles) ♦ Digital CDR Mode: !system_reset && RXLOCK == 1 “RX Reset Sequence Background,” page 100 for information on the 16K REFCLK cycles requirement. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 86: Figure 2-14: Flow Chart Of Tx Reset Sequence Where Tx Buffer Is Used

    TX_SYSTEM_RESET: Upon TX system reset on this block, go to the TX_PMA_RESET state. TXPMARESET == 0 TXRESET == 0 TX_PMA_RESET: Assert TXPMARESET for three TXUSRCLK cycles. TXPMARESET == 1 TXRESET == X www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 87: Figure 2-15: Resetting The Transmitter Where Tx Buffer Is Used

    TXUSRCLK TXPMARESET TXLOCK TXRESET TXBUFERR Once TXBUFERR is monitored Low for some time, TX Link is READY UG076_ch2_16_040606 Figure 2-15: Resetting the Transmitter Where TX Buffer Is Used Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 88: Figure 2-16: Flow Chart Of Tx Reset Sequence Where Tx Buffer Is Bypassed

    < 16 && tx_align_err==1 && TXLOCK==1 tx_align_err==0 && TXLOCK=1 for 64 TXUSRCLK cycles TXLOCK==0 tx_align_err==1 && TXLOCK==1 TX_READY ug076_ch2_17_060606 Figure 2-16: Flow Chart of TX Reset Sequence Where TX Buffer Is Bypassed www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 89 TX_SYSTEM_RESET: Upon TX system reset on this block, go to the TX_PMA_RESET state. TXPMARESET == 0 TXRESET == 0 TXSYNC == 0 TX_PMA_RESET: Assert TXPMARESET for three TXUSRCLK cycles. TXPMARESET == 1 TXRESET == X TXSYNC == 0 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 90 Use a free-running clock (for example, the system's clock) and make sure that the wait time for each state equals the specified number of TXUSRCLK and TXUSRCLK2 cycles. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 91: And Tx_Align_Err Is Not Used

    64 synchronization clock cycles specified in this block. • tx_usrclk_stable is a status signal from the user's application that is asserted High when both TXUSRCLK and TXUSRCLK2 clocks are stable. For example, if a DCM is Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 92 TXSYNC == 0 TX_WAIT_PCS: Wait for five TXUSRCLK cycles after deassertion of TXRESET. If TXLOCK is deasserted, go back to TX_WAIT_LOCK state. TXPMARESET == 0 TXRESET == 0 TXSYNC == 0 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 93: Figure 2-18: Resetting The Transmitter Where Tx Buffer Is Bypassed

    RXLOCK signals are asserted. It is reset when the block cycles back to the RX_PMA_RESET state. • “RX Reset Sequence Background,” page 100 for information on the 16K REFCLK cycles requirement. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 94: Figure 2-19: Flow Chart Of Receiver Reset Sequence Where Rx Buffer Is Used

    RX_SYSTEM_RESET: Upon RX system reset on this block, go to the RX_PMA_RESET state. RXPMARESET == 0 RXRESET == 0 RX_PMA_RESET: Assert RXPMARESET for three RXUSRCLK cycles. RXPMARESET == 1 RXRESET == X www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 95: Figure 2-20: Resetting The Receiver In Digital Cdr Mode Where Rx Buffer Is Used

    RXBUFERR Once RX error is monitored Low for some time, RX Link is READY ug076_ch2_21_040406 Figure 2-20: Resetting the Receiver in Digital CDR Mode Where RX Buffer Is Used Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 96: Figure 2-21: Resetting The Receiver In Analog Cdr Mode Where Rx Buffer Is Used

    16K REFCLK cycles requirement. • This RX reset sequence is for Analog CDR mode. The RX buffer bypass mode is not supported with the digital receiver. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 97: Figure 2-22: Flow Chart Of Receiver Reset Sequence Where Rx Buffer Is Bypassed

    < 16 && rx_error==1 && RXLOCK==1 rx_error==0 && RXLOCK==1 for 64 RXUSRCLK cycles RXLOCK==0 rx_error==1 && RXLOCK==1 RX_READY ug076_ch2_23_060606 Figure 2-22: Flow Chart of Receiver Reset Sequence Where RX Buffer Is Bypassed Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 98 16 times as monitored by the rx_pcs_reset_cnt counter, apply a RXPMARESET by cycling back to the RX_PMA_RESET state. RXPMARESET == 0 RXRESET == 0 RXSYNC == 0 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 99: Reset Considerations

    Both RXUSRCLK and RXUSRCLK2 must be stable before applying RXRESET. • For 8-byte external data interface widths, TXRESET should be deasserted synchronously with the falling edge of TXUSRCLK2 to ensure proper transmit data ordering. See Figure 2-24. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 100: Rx Reset Sequence Background

    Because the RX PLL is locked to the reference clock in Digital CDR mode, there is no need to assert RXLOCK High for a specific number of REFCLK cycles. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 101: Chapter 3: Pcs Digital Design Considerations

    Figure 3-1: Transmit Architecture Receive Architecture The receive architecture for the PCS is shown in Figure 3-2. For information about bypassing particular blocks, consult the block function section for that particular block. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 102: Fabric Interface Synchronicity

    The RX ring buffer goes to half-full upon initialization or reset (RXRESET = 1), as illustrated in Figure 3-3. RX Ring Buffer (Buffer overflows at > 57) (Buffer underflows at < 17) ug076_ch3_41_060107 Figure 3-3: RX Ring Buffer Half-Full Upon Initialization www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 103: Bus Interface

    1-byte and 2-byte interfaces are preferred. For higher serial rates, 4-byte and 8-byte interfaces are recommended. Table 3-2 shows the available external (fabric interface) bus width settings. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 104: Internal Bus Width Configuration

    Table 3-2: Selecting the Internal Configuration RXINTDATAWIDTH/TXINTDATAWIDTH Internal Data Width 32 bit 2’b10 40 bit 2’b11 Note: The digital receiver must also have the same data bus width controlled with RXBY_32. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 105: Fabric Interface Functionality

    Same as Cycle 0 Same as Cycle 1 Same as Cycle 3 Notes: 1. User accesses lower 4 bytes. 2. User accesses lower 2 bytes. 3. User accesses lower 1 byte Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 106: Figure 3-5: Fabric Interface Timing

    D3 D2 D1 D0 D7 D6 . . . NOTE: D7–D0 refer to data that is being received from the internal 4-byte MGT data path. ug079_ch3_28_050906 Figure 3-5: Fabric Interface Timing www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 107: Pcs Bypass Byte Mapping

    Byte 0 RXDATA[7:0] ug076_ch3_26_091406 Figure 3-7: PCS Bypass Byte Mapping, 4-Byte External Fabric Width Note: External data width of 1 and 2 bytes is not supported in this mode. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 108: 8B/10B Encoding/Decoding

    LSB 3 LSB 2 LSB 1 LSB 0 4 th Sent 3 rd Sent 2 nd Sent 1 st Sent Encoded Encoded Encoded Encoded ug076_ch3_40_041306 Figure 3-9: 4-Byte Serial Structure www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 109: Encoder

    Note that running disparity is not synchronized with the encoder when this bypass is asserted. This feature should be used only by applications that are not interested in tracking disparity errors. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 110: Txchardispval And Txchardispmode

    TXCHARDISPVAL is also set to a logic 0. However, the disparity is inverted before encoding the byte when the TXCHARDISPVAL is set to a logic 1. Most applications use the www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 111: Txcharisk

    Latency for TXKERR, in TXUSRCLK2 cycles: 4-byte fabric interface: TXRUNDISP = 4, TXKERR = 5 2-byte fabric interface: TXRUNDISP = 7, TXKERR = 9 1-byte fabric interface: TXRUNDISP = 13, TXKERR = 17 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 112: Decoder

    “h” and “j,” respectively, of the 10-bit encoded data that the transceiver passes on to the user logic. Table 3-6 illustrates the RX data map during 8B/10B bypass. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 113: Rxcharisk And Rxrundisp

    “Non-Standard Running Disparity Example,” page 115. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 114: Rxnotintable

    10-bit codes with xxx1111100. DEC_PCOMMA_DET RXCHARISCOMMA does not respond FALSE to positive-disparity commas. FALSE RXCHARISCOMMA = 1 indicates TRUE 10-bit codes with xxx0000011. DEC_MCOMMA_DET RXCHARISCOMMA does not respond FALSE to negative-disparity commas. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 115: Non-Standard Running Disparity Example

    K28.5+ (or K28.5-) CHAN_BOND_SEQ_1_3 = 0 0 1 10111100 matches K28.5- (or K28.5+) CHAN_BOND_SEQ_1_4 = 0 1 1 10111100 matches K28.5- (or K28.5+) CHAN_BOND_SEQ_LEN = 4 CHAN_BOND_SEQ_2_USE = FALSE Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 116: Symbol Alignment And Detection (Comma Detection)

    ENPCOMMAALIGN Comma alignment is enabled. The comma is defined ENMCOMMAALIGN by COMMA_10B_MASK and PCOMMA _32B_VALUE. Comma alignment is enabled. The comma is defined by COMMA_10B_MASK and MCOMMA _32B_VALUE, PCOMMA_32B_VALUE. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 117: 8-Bit / 10-Bit Alignment

    8B/10B encoding scheme) are reversed relative to Virtex-II Pro devices, but are similar to Virtex-II Pro X devices. For other generation differences, see Appendix E, “Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO Transceiver Design Migration.” 10-Bit Alignment for 8B/10B Encoded Data Figure 3-12 shows an example of Virtex-4 10-bit comma detection.

  • Page 118: Figure 3-13: 6-Bit Alignment Mux Position

    RXBLOCKSYNC64B66BUSE = 0. This is illustrated in Figure 3-13. RXUSRCLK2 RXLOSSOFSYNC[1] RXLOSSOFSYNC[0] BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 0 BIT 1 ug076_ch3_080505 Figure 3-13: 6-Bit Alignment Mux Position www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 119: Sonet Alignment

    6F6F 1414 0000 Byte-aligned A1A1A1A1A2A2A2A2 pattern = 0x6F6F6F6F14141414 rxdata_sonet_aligned[31:0] 6F6F 1414 0000 6F6F 1414 0000 Word-aligned A1A1A2A2 boundary ug076_ch3_36_061907 Figure 3-15: SONET Alignment Sequence (4-Byte External Data Interface Width) Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 120: Figure 3-16: Sonet Alignment Sequence (2-Byte External Data Interface Width)

    = hold SONET alignment mux position. ENPCOMMAALIGN Byte Aligner: = realign byte alignment mux when the A1 symbol is found on a non-byte aligned boundary. = hold alignment mux position. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 121 ENPCOMMAALIGN and ENMCOMMAALIGN together, and then turn them both off when alignment is achieved. This allows the A1 and A2 symbols to be received without alignment being affected. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 122: Alignment Status

    1 Byte Fabric IF Note: 2 Byte Fabric IF Shaded area is where the comma 4 Byte Fabric IF is placed. 8 Byte Fabric IF ug076_ch3_29_030105 Figure 3-17: Comma Placement www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 123: Rxslide

    CLK_COR_SEQ_DROP should ALWAYS be set to FALSE. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 124: Clock Correction Sequences

    The sequence contains 11 bits including the 10 bits of serial data. The 11th bit has two different formats. The typical usage is shown in Table 3-14. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 125: Clk_Cor_Seq_1_Mask, Clk_Cor_Seq_2_Mask

    Table 3-16: Clock Correction Mask Example Settings (No Mask) Attribute Setting Definition CLK_COR_SEQ_1_1 Defines a K28.5. 00110111100 CLK_COR_SEQ_1_2 Defines a D21.4. 00010010101 CLK_COR_SEQ_1_MASK Check compare first 2 bytes. 1100 CLK_COR_SEQ_LEN Complete sequence is 2 bytes. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 126: Determining Correct Clk_Cor_Min_Lat And Clk_Cor_Max_Lat

    CHAN_BOND_MODE is not OFF. For symbols of 8 bytes, (CLK_COR_MIN_LAT – CHAN_BOND_LIMIT) > 24. The defaults of 36 and 44 meet these requirements for a CHAN_BOND_LIMIT of 7. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 127: Channel Bonding

    In this mode, the master arbitrates between clock correction and channel bonding with clock correction being given priority. Clock correction requests to the arbitrator are generated by the RX pointer difference being Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 128 The channel bond sequence should not be fixed such that it repeats continuously with spacing less than the worst-case slave processing time of 9 + CHAN_BOND_LIMIT/4 (rounded up) RXUSRCLKs (36 + CHAN_BOND_LIMIT bytes). If possible, channel www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 129: Cccb_Arbitrator_Disable Attribute

    68 bytes + CHAN_BOND_LIMIT between clock correction and channel bonding sequences. Additionally, there must be a minimum of a 12 byte gap between channel bonding sequences. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 130: Chan_Bond_Seq_1_Mask, Chan_Bond_Seq_2_Mask

    Because of the delay limitations on the CHBONDO to CHBONDI ports, linking of the master to a Slave_1_Hop must run either in the X or Y direction, but not both. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 131: Figure 3-20: Daisy-Chained Transceiver Chbondi/Chbondo Buses

    CHBONDO CHBONDI CHBONDI XC4VFX20 CHBONDI SLAVE_2_HOPS SLAVE_1_HOP CHBONDI CHBONDI CHBONDO SLAVE_1_HOP SLAVE_2_HOPS CHBONDI CHBONDI SLAVE_1_HOP SLAVE_2_HOPS CHBONDI CHBONDI CHBONDO SLAVE_1_HOP SLAVE_2_HOPS CHBONDI XC4VFX60 UG076_ch3_11_061907 Figure 3-21: XC4VFX20/XC4VFX60 Device Implementation Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 132: Rx Fabric Interface And Channel Bonding

    MGT and the channel bonding master. Table 3-22: Signal Values for a Channel Bonding Skew Status RXSTATUS[5] RXSTATUS[4:3] RXSTATUS[2:0] STATUS INDICATOR 1'b0 2’b01 3’b001 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 133: Event Indication

    • Internal dividers cannot be used because each divider could independently introduce a phase shift, resulting in a phase mismatch between the PCS RXCLK and PCS TXCLK domains. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 134: Digital Receiver

    • Effectively VCO frequency = line rate × 4 • Parallel clock (PMA RXCLK0 frequency before digital receiver) = 4.976 Gb/s ÷ 40 (parallel data width) = 124.4 Mhz www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 135: Figure 3-23: Digital Receiver Example

    Because the receiver is locked to reference, the inherent frequency difference between the incoming data and the local PLL clock must be accommodated. In the Virtex-4 RocketIO transceiver, this is accomplished by modulating the recovered clock. Typically, the recovered clock is output to the FPGA fabric at the nominal frequency, but occasionally, shorter clock periods are generated.

  • Page 136: Clocking In Buffered Mode

    Note: 8-byte fabric interface is not recommended for use in combination with the digital receiver. TRUE: Chooses the asynchronous clock generated by the Digital RXRECCLK1_USE_SYNC Receiver to drive RXRECCLK1. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 137 4XCLK and consequently the RXRECLK1 that is derived from the Digital receiver. 3. Ensure that the transmitter and receiver are driven by the same clock source and use internal dividers on RXUSRCLK as shown in Figure 3-24. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 138: Www.xilinx.com Virtex-4 Rocketio Mgt User Guide Ug076 (V4.1) November 2

    Chapter 3: PCS Digital Design Considerations www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 139: Chapter 4: Pma Analog Design Considerations

    The output swing and emphasis levels of the MGTs are fully programmable. Each is controlled via attributes at configuration, but can be modified via the Dynamic Reconfiguration Port programming bus (Appendix C, “Dynamic Reconfiguration Port”). Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 140: Emphasis

    TXPRE_TAP_DAC is recommended to be small compared to the other driver settings. The post-cursor (post-driver) improves the “tail” of the pulse at the receiver. TXPOST_TAP_DAC should be less than TXDAT_TAP_DAC, so as not to destroy the pulse www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 141: Figure 4-3: Effect Of 3-Tap Pre-Emphasis On A Pulse Signal

    Table 4-2: TXDAT_TAP_DAC and TXPOST_TAP_DAC Settings Line Loss Differential Swing TXDAT_TAP_DAC TXPOST_TAP_DAC (dB) (mV) 10011 00000 11011 00010 01001 00001 10001 00101 11000 01001 01000 00100 01111 01001 10110 01111 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 142 Pre-Emphasis dB = 20 log(V The equations for calculating de-emphasis as a percentage and dB are as follows: De-Emphasis% = (V ) x 100 De-Emphasized dB = 20 log(V www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 143: Figure 4-4: Tx With Minimal Pre-Emphasis

    Output Swing and Emphasis ug076_ch4_17.eps Figure 4-4: TX with Minimal Pre-Emphasis Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 144: Figure 4-5: Rx After 36 Inches Fr4 And Minimal Pre-Emphasis

    Chapter 4: PMA Analog Design Considerations ug076_ch4_18.eps Figure 4-5: RX after 36 Inches FR4 and Minimal Pre-Emphasis www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 145: Figure 4-6: Tx With Maximal Pre-Emphasis

    Output Swing and Emphasis ug076_ch4_19.eps Figure 4-6: TX with Maximal Pre-Emphasis Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 146: Differential Receiver

    The derived clock, RXRECCLK1/RXRECCLK2, is generated and locked to as long as it remains within the specified component range. This clock is presented to the FPGA fabric www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 147: Receiver Lock Control

    The choice of RXAFEEQ setting depends on the amount of high-frequency loss in the transmission media. Links with more transmission loss should use the higher gain settings. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 148: Figure 4-8: Ac Response Of Continuous-Time Linear Receiver Equalizer

    AC Response RXAFEEQ = 111 RXAFEEQ = 011 RXAFEEQ = 001 RXAFEEQ = 000 100M freq ( Hz ) ug076_ch4_16_060107 Figure 4-8: AC Response of Continuous-Time Linear Receiver Equalizer www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 149: Special Analog Functions

    The MGT contains built-in circuitry to optimize the PLL performance. Table 4-4 Table 4-5 show the recommended calibration settings. Xilinx recommends using the RocketIO Wizard to set attributes. This wizard manages dependencies between parameters and applies design-rule checks to prevent invalid configurations.
  • Page 150 6.25% or more. In selecting the calibration and normal operation lock and hysteresis settings, always set the normal operation ranges tighter than the calibration ranges. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 151: Powerdown

    POWERDOWN, the current to TXP/TXN is turned off. The 50Ω connection to V always connected, creating the termination value. Any given MGT that is not instantiated in the design is automatically set to the POWERDOWN state by the Xilinx ISE® development software and consumes no power.

  • Page 152: Rxdccouple

    This attribute shuts off the clocks to the receiver to save power. This does not affect the PLL. TXPD This attribute shuts off the clocks to the transmitter to save power, This does not affect the PLL. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 153: Figure 5-1: 32-Bit Crc Inputs And Outputs

    CRC value. RXCRCPD Powers down RX CRC Logic when set to logic 1. RXCRCRESET Resets the RX CRC logic when set to logic 1. TXCRCCLK Transmitter CRC logic clock. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 154: Chapter 5: Cyclic Redundancy Check (Crc)

    FALSE/TRUE. Inverts the receiver CRC clock. FALSE = CRC clock not inverted (default) RXCRCINVERTGEN TRUE = CRC clock inverted. During normal operation this should always be set to FALSE. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 155: Functionality

    The data width can be changed by CRCDATAWIDTH at any time to support change in data rate and end-of-packet residue. (Packet length is assumed to be a multiple of bytes.) Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 156: Figure 5-2: 64-Bit To 32-Bit Core Interface

    1. Other data rates can be achieved by changing the frequencies of operation and effective data widths. 2. The maximum speed of these configurations is determined by the fabric speed. The maximum speed is typically about 350 MHz. 3. The maximum frequency is speed-grade specific. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 157: Handling End-Of-Packet Residue

    The CRC wakeup time is two CRCCLK clock cycles if the CRC powerdown is asynchronously asserted and deasserted with the CRCINTCLK. The CRC wakeup time is one CRCCLK clock cycle if the CRC powerdown is synchronously asserted and deasserted with the CRCINTCLK. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 158: 64-Bit Example

    -9 -8 -7 -6 -5 -4 -3 -2 -1 Internal CRCOUT [31:0] CRCOUT[31:0] Internal valid CRC values Initial CRC Output CRC ug076_ch5_04_080805 Figure 5-3: Max Data Rate Example (64-Bit) www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 159: 32-Bit Example

    1 2 3 4 CRCOUT[31:0] x x 1 2 3 4 5 Internal valid CRC at 32-bit boundary Initial CRC Output CRC ug076_ch5_05_011205 Figure 5-4: Max Data Rate Example (32-Bit) Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 160: 16-Bit Transmission, Hold Crc, And Residue Of 8-Bit Example

    1 1 2 2 3 Internal CRCOUT [31:0] CRCOUT[31:0] Internal Valid CRC at 32-Bit Boundary Initial CRC Output CRC UG076_03_090605 Figure 5-5: 16-Bit Transmission, Hold CRC, and Residue of 8-Bit Example www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 161: Implementation

    Invert CRCOUT[31:0] CRCOUT[31:0] Value to get CRC value End of Packet? Set CRCDATAWIDTH Deassert Calculate New to Remaining # CRCDATAVALID CRC Value Bytes ug076_ch5_07_102505 Figure 5-6: CRC Generation Diagram Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 162: Www.xilinx.com Virtex-4 Rocketio Mgt User Guide Ug076 (V4.1) November 2

    Chapter 5: Cyclic Redundancy Check (CRC) www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 163: Chapter 6: Analog And Board Design Considerations

    This section outlines the requirements for power filtering networks, reference, and high-speed differential clock signal traces. Designs that do not adhere to these requirements are not supported by Xilinx, Inc. Power Conditioning Each MGT has five power supply pins (AVCCAUXTX is shared between two MGTs in a tile), all of which are sensitive to noise.

  • Page 164: Figure 6-1: Mgt Tile Power And Serial I/O Pins

    REFCLK Circuitry and VTRXB Bias RXBP RXB CDR and Deserializer RXBN MGT Bias Circuits AVCCAUXMGT and MGTCLK Input Buffer UG076_ch6_07_072007 Figure 6-1: MGT Tile Power and Serial I/O Pins www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 165: Power Supply Requirements

    RocketIO transmitter or receiver is coupled to another RocketIO MGT or coupled to a transceiver from another vendor, provided the termination networks have a CML topology. Equation 6-4 Equation 6-5 are valid only when V and V are equal. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 166: Voltage Regulation

    Figure 6-2: Internal Receiver AC Coupling with External DC Coupling between Transmitter and Receiver Terminations Note: Placing a Virtex-4 RocketIO MGT in power-down mode does not disconnect the termination network; current draw from the V and V pins continues to occur. Achieving open-circuit current draw from the RocketIO MGT requires the serial data input and output lines to be completely disconnected from any circuits.

  • Page 167: Figure 6-4: Power Filtering Network For One Mgt Tile

    In cases where the MGT is interfacing with another Xilinx MGT, a 1.5V termination voltage is recommended for largest signal amplitude for longer trace lengths. However, V = 1.2V...

  • Page 168: Powering Unused Mgts

    GT11CLK_MGT or MGT, or when SYNCLK1/2 passes through that tile. Since clocking resources for each MGT tile are powered from AVCCAUXRXB and AVCCAUXMGT, careful placement of used/unused MGTs must be observed to reduce the www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 169: Figure 6-6: Optimizing Filtering For An Mgt Column

    Table 6-1 Table 6-2 show which AVCCAUXRXB and AVCCAUXMGT must be filtered for each case shown in Figure 6-6. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 170: Reference Clock

    400 MHz, the EG2121CA must be replaced with the VS500, a Voltage-Controlled Saw Oscillator (VCSO). Figure 6-8 illustrates the VCSO implementation. In addition to the filtered 3.3V supply voltage shown, the VCSO also requires a control voltage (not shown). www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 171: Termination

    Figure 6-9: Transmit Termination The receiver termination supply (V ) is the center tap of differential termination to RXP and RXN, as shown in Figure 6-10. This supports multiple termination styles, including Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 172: Ac And Dc Coupling

    The on-chip AC coupling supports DC-balanced data for the entire range of data rates (622 Mb/s – 6.5 Gb/s). DC-balanced coding ensures that the coupling capacitor does not charge up or down, thus leaving the common mode voltage at an optimal value. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 173: Figure 6-11: Ac-Coupled Serial Link

    Physical Requirements 0DIFF 0DIFF 0DIFF Note: When using an external capacitor on a Virtex-4 RocketIO transmitter, and V , one-third of the maximum differential signal swing is lost. ug076_ch4_06_092606 Figure 6-11: AC-Coupled Serial Link The internal AC coupling provides a high-pass filter with a corner frequency of 40.8 kHz.

  • Page 174: Selectio-To-Mgt Crosstalk

    1.0 mm column. In addition, the table also lists those pins which have package core vias which are adjacent to analog supply package core vias. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 175 C7, C9, C12, C14 – – – Notes: 1. MGT_101 and MGT_114 only for XC4VFX100-FF1152 2. MGT_106 and MGT_109 only for XC4VFX60-FF1152 and XC4VFX100-FF1152 3. Pins in BOLD are no-connects for XC4VFX40-FF1152 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 176: High-Speed Serial Trace Design

    3 Gb/s. For frequencies up to 6 Gb/s, a maximum difference in trace length of 10 mils is recommended. Use SI CAD tools to confirm these assumptions on specific board designs. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 177: Differential Trace Design

    (increase the individual trace width where trace separation occurs). Figure 6-16 Figure 6-17 show examples of PCB geometries that result in 100Ω differential impedance. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 178: Figure 6-15: Obstacle Route Geometry

    = 10.0 mil (0.254 mm) = 10.0 mil (0.254 mm) Trace Trace = 64.8Ω = 64.8Ω = 100Ω 0DIFF Dielectric = 4.3 Reference Plane ug035_ch4_21_022703 Figure 6-17: Stripline Edge-Coupled Differential Pair www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 179: Chapter 7: Simulation And Implementation

    The SmartModel must be installed in a SmartModel-capable simulator before it can be used. This can be accomplished using the same compxlib utility that installs other Xilinx simulation libraries, such as UNISIMS and SIMPRIMS.

  • Page 180: Hspice

    Three TX/RXUSRCLKs should be sufficient in all cases. Five TX/RXUSRCLK cycles are needed to allow the reset to be deasserted internally. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 181: Out-Of-Band (Oob) Signaling

    The simulation behavior of this signals is modeled using the glbl module in Verilog and the ROC/ROCBUF components in VHDL. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 182: Simulating In Verilog

    Simulating in Verilog The global set/reset (GSR) and global 3-state (GTS) signals are defined in the $XILINX/verilog/src/glbl.v module. The glbl.v module connects the global signals to the design, which is why it is necessary to compile this module with the other design files and load it along with the design.v and testfixture.v files for...
  • Page 183 <= '1', '0' after CLK_PERIOD * 30; SRP <= '1', '0' after CLK_PERIOD * 25; For further details, refer to the software user manual Synthesis and Verification Design Guide available at http://www.xilinx.com/support/sw_manuals/xilinx7/download/. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 184: Phase-Locked Loop

    4-byte interface: TX_DATA [31:24] → USER_8B_TX_DATA [7:0] TX_DATA [23:16] → USER_8B_ TX_DATA [15:8] TX_DATA [15:8] → USER_8B_ TX_DATA [23:16] TX_DATA [7:0] → USER_8B_ TX_DATA [31:24] www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 185: Mgt Ports That Cannot Be Simulated

    ♦ TXSYNC ♦ RXSYNC Note: RXMCLK clock port is not supported. TXBUFFERR If an assertion of TXBUFFERR occurs, it is most likely that the clock attributes were set incorrectly. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 186: Transceiver Location And Package Pin Relation

    – – – 113A 112A GT11_X1Y6 – – – – – – – – – – 113B GT11_X1Y7 – – – – – – – – – – 113A www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 187 – – – 113A 113A GT11_X1Y8 – – – – – – – – – – 114B GT11_X1Y9 – – – – – – – – – – 114A Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 188 GT11_X1Y5 112A 111A GT11_X1Y6 113B 112B GT11_X1Y7 113A 112A GT11_X1Y8 114B 113B GT11_X1Y9 114A 113A GT11_X1Y10 – – – – – 114B GT11_X1Y11 – – – – – 114A www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 189 AF21 AP28 AP29 GT11CLK_X0Y2 – – – – – – GT11CLK_X0Y3 GT11CLK_X1Y0 – – – – – – GT11CLK_X1Y1 AF11 AF10 GT11CLK_X1Y2 – – – – – – GT11CLK_X1Y3 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 190 – – – GT11CLK_X0Y1 AW33 AW34 GT11CLK_X0Y2 – – – GT11CLK_X0Y3 – – – GT11CLK_X0Y4 GT11CLK_X1Y0 – – – GT11CLK_X1Y1 GT11CLK_X1Y2 – – – GT11CLK_X1Y3 – – – GT11CLK_X1Y4 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 191: Chapter 8: Low-Latency Design

    TXDATA_SEL = 00 — full data path • TXDATA_SEL = 01 — data directly from fabric interface • TXDATA_SEL = 10 — data directly from output of 8B/10B encoder Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 192: Pcs Clocking Domains And Data Paths

    Clock RXRECCLK2 Control ENMCOMMAALIGN RXBLOCKSYNC64B66BUSE, RXDEC8B10BUSE, RX_BUFFER_USE RXDEC64B66BUSE, ENPCOMMAALIGN RXCOMMADETUSE RXDESCRAM64B66BUSE RXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_01_061507 Figure 8-1: PCS Receive Clocking Domains and Data Paths www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 193: Transmitter

    10GBASE-R 1100 TXCHARISK Encode Scrambler ETC. TXENC8B10BUSE, TXSCRAM64B66BUSE, TX_BUFFER_USE TXENC64B66BUSE TXGEARBOX64B66BUSE, TXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_02_071807 Figure 8-2: PCS Transmit Clocking Domains and Data Paths Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 194: Pcs Data Path Latency

    1-byte mode USRCLK2:USRCLK ratio = 4:1 b. 2-byte mode USRCLK2:USRCLK ratio = 2:1 c. 4-byte mode USRCLK2:USRCLK ratio = 1:1 d. 8-byte mode USRCLK2:USRCLK ratio = 1:2 7. 64B/66B encoding/decoding is not supported. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 195 40 UI, depending on internal datapath width. 5. These delays include a registered data mux, which accounts for one clock of delay. 6. 64B/66B encoding/decoding is not supported. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 196: Ports And Attributes

    1. 64B/66B encoding/decoding is not supported. 2. PCS RXCLK is the RX PCS parallel clock, the RX buffer read clock. Refer to “Attributes” in Chapter 1 Figure 2-7, page 74 for more details. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 197: Transmitter

    TX PMA or RX PMA to synchronize the PCS and PMA clocks. This operation should be performed only after the PLL is locked. See “Resets” in Chapter 2 for more details on establishing lock. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 198: Transmit Latency And Output Skew

    TXUSRCLK port. This could require the use of an additional DCM or PMCD. Note: If using a DCM, only CLK0 and CLKDV outputs should be used. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 199: Use Models

    Reset TXRESET across multiple channels should always be synchronized to minimize skew across channels. Refer to section “Resets” in Chapter 2 for details on resetting multiple channels. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 200: Tx Low Latency Buffered Mode With Channel Deskew

    Clock Domain Clock Domain PMA Sync Phase Clock Align Clock Dividers TXUSRCLK2 Dividers TX RING TXCLK0 BUFFER TXUSRCLK ug076_ch8_03_050906 Figure 8-3: Using GREFCLK as Synchronization Clock (Use Models TX_2A-H) www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 201: Use Models

    Dynamic Reconfiguration Port. Alternatively, this can be achieved by adding the constraint TXCLK0_INVERT_PMALEAF = "TRUE" to the UCF file. The COREGen RocketIO Wizard generates this constraint when choosing to bypass the buffer to enable Low Latency. 5. 64B/66B encoding/decoding is not supported. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 202: Figure 8-4: Tx Low Latency Buffered Mode: Use Models Tx_1A, Tx_2A

    TXCHARISK Encode Scrambler ETC. TXENC8B10BUSE, TXSCRAM64B66BUSE, TX_BUFFER_USE TXENC64B66BUSE TXGEARBOX64B66BUSE, TXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_04_071807 Figure 8-4: TX Low Latency Buffered Mode: Use Models TX_1A, TX_2A www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 203: Figure 8-5: Tx Low Latency Buffered Mode: Use Models Tx_1B, Tx_2B

    TXCHARISK Encode Scrambler ETC. TXENC8B10BUSE, TXSCRAM64B66BUSE, TX_BUFFER_USE TXENC64B66BUSE TXGEARBOX64B66BUSE, TXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_05_071807 Figure 8-5: TX Low Latency Buffered Mode: Use Models TX_1B, TX_2B Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 204: Figure 8-6: Tx Low Latency Buffered Mode: Use Models Tx_1C, Tx_2C

    TXCHARISK Encode Scrambler ETC. TXENC8B10BUSE, TXSCRAM64B66BUSE, TX_BUFFER_USE TXENC64B66BUSE TXGEARBOX64B66BUSE, TXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_06_071907 Figure 8-6: TX Low Latency Buffered Mode: Use Models TX_1C, TX_2C www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 205: Figure 8-7: Tx Low Latency Buffered Mode: Use Models Tx_1D, Tx_2D

    TXCHARISK Encode Scrambler ETC. TXENC8B10BUSE, TXSCRAM64B66BUSE, TX_BUFFER_USE TXENC64B66BUSE TXGEARBOX64B66BUSE, TXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_07_071907 Figure 8-7: TX Low Latency Buffered Mode: Use Models TX_1D, TX_2D Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 206: Figure 8-8: Tx Low Latency Buffered Mode: Use Model Tx_2E

    1100 TXCHARISK Encode Scrambler ETC. TXENC8B10BUSE, TXSCRAM64B66BUSE, TX_BUFFER_USE TXENC64B66BUSE TXGEARBOX64B66BUSE, TXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_19_071907 Figure 8-8: TX Low Latency Buffered Mode: Use Model TX_2E www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 207: Figure 8-9: Tx Low Latency Buffered Mode: Use Model Tx_2F

    1100 TXCHARISK Encode Scrambler ETC. TXENC8B10BUSE, TXSCRAM64B66BUSE, TX_BUFFER_USE TXENC64B66BUSE TXGEARBOX64B66BUSE, TXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_20_071907 Figure 8-9: TX Low Latency Buffered Mode: Use Model TX_2F Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 208: Figure 8-10: Tx Low Latency Buffered Mode: Use Model Tx_2G

    1100 TXCHARISK Encode Scrambler ETC. TXENC8B10BUSE, TXSCRAM64B66BUSE, TX_BUFFER_USE TXENC64B66BUSE TXGEARBOX64B66BUSE, TXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_21_071907 Figure 8-10: TX Low Latency Buffered Mode: Use Model TX_2G www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 209: Skew

    To ensure this, the TXRESET should be deasserted on the negative edge of TXUSRCLK. Refer to section “Resets” in Chapter 2 for details on resetting multiple MGTs to minimize skew. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 210: Tx Low Latency Buffer Bypass Mode

    • If 2-byte mode is required, TX_CLOCK_DIVIDER = 01 • If 1-byte mode is required, TX_CLOCK_DIVIDER = 10 An external TXUSRCLK cannot be used in low-latency buffer bypass mode. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 211: Use Models

    Dynamic Reconfiguration Port. Alternatively, this can be achieved by adding the constraint TXCLK0_INVERT_PMALEAF = "TRUE" to the UCF file. The COREGen RocketIO Wizard generates this constraint when choosing to bypass the buffer to enable Low Latency. 6. 64B/66B encoding/decoding is not supported. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 212: Figure 8-13: Tx Low Latency Buffer Bypass Mode: Use Model Tx_3A

    Encode Scrambler ETC. TXRESET TXENC8B10BUSE, TXSCRAM64B66BUSE, TX_BUFFER_USE TXENC64B66BUSE TXGEARBOX64B66BUSE, TXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_09_071907 Figure 8-13: TX Low Latency Buffer Bypass Mode: Use Model TX_3A www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 213: Skew

    Therefore, the first sweep is variable in length, depending on the initial relationship of the two clocks. The second sweep takes either 16 or 20 adjustments, according to the Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 214: Timing

    The TXSYNC port must remain asserted for the entire phase alignment process. TXSYNC must be asserted for least 64 synchronization clock cycles (TSYNC). b. The synchronization clock (alignment reference) can be GREFCLK or PCS TXCLK. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 215: Tx Channel Skew Using Txsync

    MGTs. For 4-byte fabric width, there is no divider, so the skew is 0. For 2-byte and 1-byte mode, the skew in UI depends on the internal datapath used: Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 216: Synchronization Clock = Grefclk, Txphasesel = False

    FPGA. User must also account for skew on the board and at the receiver end to determine the total skew seen at the receiver. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 217: Tx Skew Estimation Examples

    5.1849UI 6.5 Gbit/s, Synchronization Clock = GREFCLK, TXPHASESEL = FALSE 100 ps 70 ps ---------------------- - UI 0UI TXSkew ---------------------- - worstcase 153.85 ps 153.85 ps 0.6500UI 0.4550UI 3.1050UI Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 218 1. 1-byte mode is not supported for 3.125 Gb/s data rate, and 1-byte and 2-byte modes are not supported for 6.5 Gb/s data rate, because fabric interface speed is limited to 250 MHz. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 219: Rx Latency

    Set RX_CLOCK_DIVIDER = 00 and provide the appropriate frequency clock at the RXUSRCLK port. This might require the use of an additional DCM or PMCD. • Set RXCLK0_FORCE_PMACLK to FALSE. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 220: Use Models

    “Clocking,” page 219. When using the internal PCS dividers, only Pre-Driver Serial Loopback or Normal Operation are possible. Parallel Loopback is not supported. 3. 64B/66B encoding/decoding is not supported. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 221: Figure 8-16: Rx Low Latency Buffered Mode: Use Model Rx_1A

    RXRECCLK2 Control ENMCOMMAALIGN RXBLOCKSYNC64B66BUSE, RXDEC8B10BUSE, RX_BUFFER_USE RXDEC64B66BUSE, ENPCOMMAALIGN RXCOMMADETUSE RXDESCRAM64B66BUSE RXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_12_071907 Figure 8-16: RX Low Latency Buffered Mode: Use Model RX_1A Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 222: Figure 8-17: Rx Low Latency Buffered Mode: Use Model Rx_1B

    RXRECCLK2 Control ENMCOMMAALIGN RXBLOCKSYNC64B66BUSE, RXDEC8B10BUSE, RX_BUFFER_USE RXDEC64B66BUSE, ENPCOMMAALIGN RXCOMMADETUSE RXDESCRAM64B66BUSE RXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_13_071907 Figure 8-17: RX Low Latency Buffered Mode: Use Model RX_1B www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 223: Reset

    RXRESET should be synchronized across channels to ensure that all the RX buffer pointers are in phase with each other. Refer to section “Resets” in Chapter 2 for more details. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 224: Rx Low Latency Buffer Bypass Mode

    2. RXSYNC functionality must be used in order to sync the PCS/PMA clocks. 3. Because the internal PCS dividers are used, Parallel Loopback and Channel Bonding are not supported. 4. 64B/66B encoding/decoding is not supported. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 225: Figure 8-19: Rx Low Latency Buffer Bypass Mode: Use Model Rx_2A

    Control ENMCOMMAALIGN RXBLOCKSYNC64B66BUSE, RXDEC8B10BUSE, RX_BUFFER_USE RXDEC64B66BUSE, ENPCOMMAALIGN RXCOMMADETUSE RXDESCRAM64B66BUSE RXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_15_071907 Figure 8-19: RX Low Latency Buffer Bypass Mode: Use Model RX_2A Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 226: Figure 8-20: Rx Low Latency Buffer Bypass Mode: Use Model Rx_2B

    Control ENMCOMMAALIGN RXBLOCKSYNC64B66BUSE, RXDEC8B10BUSE, RX_BUFFER_USE RXDEC64B66BUSE, ENPCOMMAALIGN RXCOMMADETUSE RXDESCRAM64B66BUSE RXDATA_SEL Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_16_071907 Figure 8-20: RX Low Latency Buffer Bypass Mode: Use Model RX_2B www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 227: Reset

    Note: (1) 64B/66B encoding/decoding is not supported. ug076_ch8_17_071907 Figure 8-21: RX Low Latency Buffer Bypass Mode: Use Model RX_2C Reset Refer to section “Resets” in Chapter 2 for more details. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 228: Rxsync

    Although the RXSYNC port is asynchronous to RXUSRCLK2, the user can simply generate RXSYNC in the RXUSRCLK2 domain and apply the RXSYNC signal to all MGTs involved in the RX phase alignment. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 229: Restrictions On Low Latency Buffer Bypass Modes

    64B/66B is not supported because the low-latency buffer bypass modes are incompatible with the gearbox and blocksync functionality. In PCS bypass mode, external data width of 1 byte and 2 bytes are not supported. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 230: Example Of A Reduced-Latency System

    The worst-case skew (Table 8-10) increases to ~23.5313 UI (~7.53 ns). The latency, however, according to Table 8-1 Figure 8-13, page 212, reduces to 85.76 ns, a significant savings. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 231 Since this is a channel-bonded system, the RX buffer should be used. From a system perspective, a user might decide not to use clock correction in order to minimize latency, using the RXRECCLK1/RXRECCLK2 to clock the RXUSRCLK and RXUSRCLK2 ports. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 232 + 0 RXUSRCLK (Data Mux) 64B/66B Format (Bypass) 0 RXUSRCLK Fabric Interface (2 Byte) 1 RXUSRCLK + 2 RXUSRCLK2 25.60 Total: 115.20 Notes: 1. 64B/66B encoding/decoding is not supported. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 233: Board Level Design

    Section II: Board Level Design Virtex-4 RocketIO Multi-Gigabit Transceiver...
  • Page 234 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 235: Chapter 9: Methodology Overview

    Chapter 9 Methodology Overview Introduction Xilinx, in partnership with Dr. Howard Johnson, has developed a two-part DVD tutorial on signal integrity techniques and loss budgeting for RocketIO transceivers. [Ref 2] These DVDs cover in more detail much of the material in...

  • Page 236: Powering The Rocketio Mgts

    A high-quality crystal oscillator is essential for good performance. When using one of the recommended oscillators, the manufacturer’s power supply design guide must be followed. Virtex-4 device characterization is based on the same recommended oscillators. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 237: Clock Traces

    With one source and one sink for each trace, the presence of branches causing reflections and degrading clock quality is removed. Xilinx recommends ICS 8543BG as a high-speed clock buffer for clock distribution to both left and right column reference clock inputs.
  • Page 238 RC time constant. Choosing capacitors with values much higher than required can introduce more surge currents during board hot-swaps. Such surge currents can stress MGT circuits. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 239: Chapter 10: Pcb Materials And Traces

    Permittivity (also known as the Dielectric Constant), and Loss Tangent. Skin effect, which causes loss from the metal conductor, is also a contributor to energy loss at line speeds in the gigahertz range. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 240: Relative Permittivity

    The choice of substrate material depends on the total length of the high-speed trace and also the signaling rate. For more information on the transmission lengths possible at various speeds and with various materials, refer to the Virtex-4 RocketIO Multi-Gigabit Transceiver Characterization Report.

  • Page 241: Traces

    In this case, the differential traces must be designed to have an odd mode impedance (Z ) of 50Ω, resulting in a differential impedance (Z ) of 100Ω, because DIFF = 2 x Z DIFF Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 242: Figure 10-1: Differential Edge-Coupled Centered Stripline

    UG072_c3_26_102005 Figure 10-4: Differential Microstrip Obtain dielectric material properties from the PCB manufacturer. Then, using either an equation or simulation tool (preferred), compute the line widths required for the www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 243: Trace Routing

    (AC sweep) and time-domain simulations (transient run). Therefore, it is important to check that the models accurately reflect actual losses. One method is to compare the models against known published configurations. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 244: Cable

    However, there could be substantial levels of crosstalk within the connector region. Optimal Cable Length Xilinx provides HSPICE models of the transceiver. Designers can use these models with vendor-supplied cable models to select the appropriate cable for their systems. Skew Between Conductors When selecting a cable, look for a specification of the skew between the conductors in a cable.

  • Page 245: Chapter 11: Design Of Transitions

    TDR port. If the signal propagation speed through the transmission line is known, the location of the excess capacitance or inductance along the channel can be calculated. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 246: Figure 11-1: Tdr Signature Of Shunt Capacitance

    TDR area. Since this is a negative reflection, in this case excess capacitance is computed. Shaded area goes into the integral for Equation 11-1 UG072_c3_13_050206 Figure 11-3: Integration of Normalized TDR Area www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 247: Figure 11-4: 2D Field Solver Analysis Of 5 Mil Trace And 28 Mil Pad

    28 Mil Pad - L = 241 nH/m - C = 89 pF/m - Zo = 52Ω UG072_c3_15_102505 Figure 11-5: Transition Optimization Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 248: Figure 11-6: Ansoft Hfss Model Of Capacitor With A Pad Clear-Out

    Figure 11-8 shows good fit to the frequency response of a lumped capacitor. Uncleared Planes Cleared Planes Frequency, GHz UG072_c3_17_102805 Figure 11-7: Return Loss Comparison Between 0402 Pad Structures www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 249: On Log (Frequency) Scale

    840 fF excess capacitance, and the cleared pads have 70 fF excess capacitance. Time, ns UG072_c3_28_102805 Figure 11-9: TDR Results Comparing 0402 Pad Structures with Excess Capacitance Reduced from 840 fF to 70 fF Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 250: Differential Vias

    11 (left side) and long stubs below layer 6 (right side). The analysis results of these models is shown in Figure 11-12, which compares the S-parameter return loss for common-mode (SCC11) and differential (SDD11) responses. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 251: Figure 11-11: Differential Gssg Via In 16-Layer Pcb From Pins L11 And L6

    GSSG vias, even long via stubs only double at most (less than a +6 dB shift) the differential via’s capacitance. Chapter 12, “Guidelines and Examples” provides additional examples of differential vias. Appendix D of the XFP SPecification [Ref 4] also provides example differential via designs. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 252: Microstrip/Stripline Bends

    However, even without widening the lines, the characteristics of the corners and jog-outs are still overly capacitive; therefore, the uncoupled section of the jog-out must not be widened. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 253: Figure 11-14: Simulated Tdr Of 45 Degree Bends With Jog-Outs

    Figure 11-14: Simulated TDR of 45 Degree Bends with Jog-Outs With jog-outs With both jog-outs and cut-outs 1E10 5E10 Frequency, Hz UG072_c3_37_050206 Figure 11-15: Simulated Return Loss of 45 Degree Bends with Jog-Outs Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 254: Figure 11-16: Simulated Phase Response Of 45 Degree Bends With Jog-Outs

    4.125 ps, which agrees well with the model. On the right side are the measured TDR results for the structure with the jog-outs where the P/N skew has been decreased substantially. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 255: Bga Packages

    100 fF to 250 fF. The longest package paths have some insertion loss, less than 1 dB worst-case at 5 GHz. To allow full simulation of package effects, the Xilinx Signal Integrity Simulation kit for Virtex-4 FPGAs provides extracted S-parameter models of the package.

  • Page 256: Www.xilinx.com Virtex-4 Rocketio Mgt User Guide Ug076 (V4.1) November 2

    Chapter 11: Design of Transitions Xilinx uses Rosenberger SMA connectors almost exclusively on our evaluation boards because of their excellent performance and because of the points listed in the previous paragraph. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 257: Chapter 12: Guidelines And Examples

    To further limit excess capacitance in vias, the unused pads on vias should be removed and the via stub length is kept to a minimum. By routing from the top microstrip to the bottom Virtex-4 RocketIO MGT User Guide www.xilinx.com...

  • Page 258: Figure 12-1: Differential Via Dimensions

    (a short stub) c) a stripline exit about one-third along the via length ( a long stub) www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 259 -0.002 -0.007 -0.017 -0.029 -0.047 -17.5 -0.078 -0.319 -0.757 -1.438 -2.554 -24.5 -0.015 -0.062 -0.141 -0.251 -0.403 -20.6 -0.038 -0.153 -0.354 -0.645 -1.067 -30.0 -0.004 -0.017 -0.039 -0.069 -0.110 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 260 This example assumes a 6 Gb/s application and the choice of using either an expensive connector with a 200 fF launch or a less expensive connector with a 400 fF launch. A board www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 261: Figure 12-2: Bga Escape Design Example

    This impact occurs when SIO solder balls are adjacent to MGT analog supply screwballs and their corresponding PCB vias are adjacent as well, creating both a package and board coupling mechanism. The screwballs, which are part of the package, offer some Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 262: Figure 12-3: Via Structures For Bga Adjacent Sio

    Figure 12-4 shows a XENPAK70 connector entry. Due to space constraints on this board and the connector mounting hole, differential vias other than the preferred GSSG-type differential via are used. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 263: Figure 12-4: Xenpak70 Connector Design Example

    As with the Xenpak70 design and other SMT designs, the planes are cleared to a depth of 30 mils for higher data rate applications. Loss simulation results are shown in Figure 12-6. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 264: Figure 12-5: Smt Xfp Connector Design Example

    For backplane applications, in-line connectors such as the one shown in Figure 12-7, are the most common. Of these connectors, the most common mounting method is press-fit, although SMT connectors offer much better performance. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 265: Figure 12-7: Tyco Z-Pack Hm-Zd Press-Fit Connector

    The right-angle connectors have P/N length differences in the signal paths, as shown in Figure 12-8, that require PCB trace lengths to be adjusted to compensate for the skew. UG072_c3_45_102605 Figure 12-8: Tyco Z-PACK HM-Zd Press-Fit Connector Internals Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 266: Figure 12-9: Tyco Z-Pack Hm-Zd Press-Fit Connector Design Example

    The reduced trace width causes additional line loss and inter- symbol interference (ISI) effects from the greater impedance variation. These effects can be offset by the additional performance gained from larger antipads with less excess capacitance. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 267: Smt Dc Blocking Capacitor Design Example

    40 mil pitch and clear the plane to a depth of about 10 mils. The capacitor pairs are also staggered to reduce crosstalk by allowing for increased separation from adjacent capacitor pairs. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 268: Www.xilinx.com Virtex-4 Rocketio Mgt User Guide Ug076 (V4.1) November 2

    Chapter 12: Guidelines and Examples www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 269: Appendixes

    Section III: Appendixes Virtex-4 RocketIO Multi-Gigabit Transceiver...
  • Page 270 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 271: Appendix A: Rocketio Transceiver Timing Model

    Use it in conjunction with the Virtex-4 data sheet and the Timing Analyzer (TRCE) report from Xilinx software. For specific timing parameter values, refer to the data sheet. There are many signals entering and exiting the MGT core. (Refer to Figure A-2.) The...
  • Page 272 Clocks receiver data and status between the transceiver and the FPGA core. Typically the same as TXUSRCLK2. Relationship between RXUSRCLK2 RXUSRCLK2 and RXUSRCLK depends on width of receiver data path. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 273: Figure A-1: Rocketio Multi-Gigabit Transceiver Block Diagram

    Notes: (1) 64B/66B encoding/decoding is not supported. (2) TXPCSHCLKOUT and RXPCSHCLKOUT ports are not supported. (3) RXCALFAIL, RXCYCLELIMIT, TXCALFAIL, and TXCYCLELIMIT ports are not supported. ug076_apA_01_071707 Figure A-1: RocketIO Multi-Gigabit Transceiver Block Diagram Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 274: Timing Parameters

    = REF (REFCLK) TX (TXUSRCLK) TX2 (TXUSRCLK2) RX (RXUSRCLK) RX2 (RXUSRCLK2) Pulse Width (Examples): Minimum pulse width, TX2 clock, Low state TX2PWL Minimum pulse width, Reference clock, High state REFPWH www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 275: Figure A-2: Mgt Timing Relative To Clock Edge

    “RocketIO TXCRCCLK Switching Characteristics,” page 277 • Table A-5, “RocketIO RXUSRCLK2 Switching Characteristics,” page 278 • Table A-6, “RocketIO RXUSRCLK2 Switching Characteristics,” page 278 • Table A-7, “RocketIO TXUSRCLK Switching Characteristics,” page 280 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 276 _RXCRCIN/ GT11DCK Data Input RXCRCIN _RXCRCIN GT11CKD _RXCRCINIT/ GT11DCK Control Input RXCRCINIT _RXCRCINIT GT11CKD _RXCRCPD/ GT11DCK Control Input RXCRCPD _RXCRCPD GT11CKD Clock to Out _RXCRCOUT Data Output RXCRCOUT GT11CKO www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 277 Relative to Clock (RXUSRCLK) Control Input CHBONDI _CHBI/T _CHBI CCCK CCKC Clock to Out Control Output CHBONDO _CHBO GCKCO Clock Minimum Pulse RXUSRCLK GPWH Width, High Minimum Pulse RXUSRCLK GPWL Width, Low Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 278 GT11CKD _RXSLIDE/ GT11DCK Control Input RXSLIDE _RXSLIDE GT11CKD _RXUSRLOCK/ GT11DCK Control Input RXUSRLOCK _RXUSRLOCK GT11CKD _RXUSRVCOCAL/ GT11DCK Control Input RXUSRVCOCAL _RXUSRVCOCAL GT11CKD _RXUSRVCODAC/ GT11DCK Control Input RXUSRVCODAC _RXUSRVCODAC GT11CKD www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 279 In a back-annotated timing simulation and in a static timing analysis, the user might see timing violations if these signals are not synchronous to RXUSRCLK2. b. The user can safely ignore these timing violations. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 280 GT11CKD _TXPMARESET/ GT11DCK Control Input TXPMARESET _TXPMARESET GT11CKD _TXPOLARITY/ GT11DCK Control Input TXPOLARITY _TXPOLARITY GT11CKD _TXSCRAM64B66BUSE/ GT11DCK Control Input TXSCRAM64B66BUSE _TXSCRAM64B66BUS GT11CKD _TXSYNC/ GT11DCK Control Input TXSYNC _TXSYNC GT11CKD www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 281 In a back-annotated timing simulation and in a static timing analysis, the user might see timing violations if these signals are not synchronous to TXUSRCLK2. b. The user can safely ignore these timing violations. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 282 Appendix A: RocketIO Transceiver Timing Model www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 283: Valid Data And Control Characters

    100100 1011 D17.0 000 10001 100011 1011 100011 0100 D18.0 000 10010 010011 1011 010011 0100 D19.0 000 10011 110010 1011 110010 0100 D20.0 000 10100 001011 1011 001011 0100 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 284: Appendix B: 8B/10B Valid Characters

    010011 1001 D19.1 001 10011 110010 1001 110010 1001 D20.1 001 10100 001011 1001 001011 1001 D21.1 001 10101 101010 1001 101010 1001 D22.1 001 10110 011010 1001 011010 1001 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 285 001011 0101 D21.2 010 10101 101010 0101 101010 0101 D22.2 010 10110 011010 0101 011010 0101 D23.2 010 10111 111010 0101 000101 0101 D24.2 010 11000 110011 0101 001100 0101 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 286 011010 0011 D23.3 011 10111 111010 0011 000101 1100 D24.3 011 11000 110011 0011 001100 1100 D25.3 011 11001 100110 1100 100110 0011 D26.3 011 11010 010110 1100 010110 0011 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 287 001100 1101 D25.4 100 11001 100110 1101 100110 0010 D26.4 100 11010 010110 1101 010110 0010 D27.4 100 11011 110110 0010 001001 1101 D28.4 100 11100 001110 1101 001110 0010 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 288 010110 1010 D27.5 101 11011 110110 1010 001001 1010 D28.5 101 11100 001110 1010 001110 1010 D29.5 101 11101 101110 1010 010001 1010 D30.5 101 11110 011110 1010 100001 1010 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 289 001110 0110 D29.6 110 11101 101110 0110 010001 0110 D30.6 110 11110 011110 0110 100001 0110 D31.6 110 11111 101011 0110 010100 0110 D0.7 111 00000 100111 0001 011000 1110 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 290 001001 1110 D28.7 111 11100 001110 1110 001110 0001 D29.7 111 11101 101110 0001 010001 1110 D30.7 111 11110 011110 0001 100001 1110 D31.7 111 11111 101011 0001 010100 1110 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 291 K27.7 111 11011 110110 1000 001001 0111 K29.7 111 11101 101110 1000 010001 0111 K30.7 111 11110 011110 1000 100001 0111 Notes: 1. Used for testing and characterization only. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 292 Appendix B: 8B/10B Valid Characters www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 293: Appendix C: Dynamic Reconfiguration Port

    Dynamic Reconfiguration Port enable when set to a logic 1 Dynamic reconfiguration input data bus Dynamic reconfiguration output data bus DRDY Strobe that indicates read/write cycle is complete Dynamic reconfiguration write enable when set to a logic 1 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 294: Memory Map

    Address RESERVED CLK_COR__8B10B_DE CLK_CORRECT_USE RESERVED CLK_COR_SEQ_LEN [7:0] [2:0] CLK_COR_SEQ_DROP RESERVED CLK_COR_SEQ_2_USE RXCRCINITVAL RESERVED [14:0] [15:0] [15:0] COMMA32 TXCLK0_INVERT_PMALEAF PCOMMA_DETECT RESERVED MCOMMA_DETECT DEC_VALID_COMMA_ONLY DEC_PCOMMA_DETECT CLK_COR_MAX_LAT [5:0] DEC_MCOMMA_DETECT ALIGN_COMMA_WORD [1:0] TXPD www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 295 RXLKAPD RXRSDPD RXRCPPD RXRPDPD RXAFEPD RXPD Notes: 1. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 296 1. The default X depends on the operation. See Table C-28, page 320 for details. 2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 297 DCDR_FILTER [2:0] COMMA_10B_MASK [9:0] RXUSRDIVISOR [4:0] Notes: 1. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 298 “Receive Equalization” in Chapter 4 for details. Note that in a UCF file RXAFEEQ must be specified as a 9-bit value. The RXAFEEQ[8:3] bits are unused and can be set to 0. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 299 1. The default X depends on the operation. See Table C-28, page 320 for details. 2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 300 1. The default X depends on the operation. See Table C-28, page 320 for details 2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 301 Table C-9: Dynamic Reconfiguration Port Memory Map: MGTA Address 63–67 Address CLK_COR_SEQ_2_2 CLK_COR_SEQ_1_2 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_1_2 [4:0] [4:0] [4:0] [4:0] RESERVED [15:0] CLK_COR_SEQ_2_1 CLK_COR_SEQ_1_1 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_1_1 [10:0] [10:0] [11:0] [11:0] Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 302 3. Although there is an open-loop divider for each MGT, both attributes map into MGTA locations in the DRP Memory Map: TXOUTDIV2SEL (for MGTB) Reg 0x6A [14:11] TXOUTDIV2SEL (for MGTA) Reg 0x7A [15:12] www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 303 DRP. 3. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 304 1. The default X depends on the operation. See Table C-28, page 320 for details. 2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 305 3. Although there is an open-loop divider for each MGT, both attributes map into MGTA locations in the DRP Memory Map: TXOUTDIV2SEL (for MGTB) Reg 0x6A [14:11] TXOUTDIV2SEL (for MGTA) Reg 0x7A [15:12] Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 306 DRP. 3. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 307 Table C-15: Dynamic Reconfiguration Port Memory Map: MGTB Address 40–44 Address RESERVED CLK_COR__8B10B_DE CLK_CORRECT_USE RESERVED CLK_COR_SEQ_LEN [7:0] [2:0] CLK_COR_SEQ_DROP CLK_COR_SEQ_2_USE RXCRCINITVAL RESERVED RXEQ [15:0] [15:0] [15:0] COMMA32 TXCLK0_INVERT_PMALEAF PCOMMA_DETECT RESERVED MCOMMA_DETECT DEC_VALID_COMMA_ONLY DEC_PCOMMA_DETECT CLK_COR_MAX_LAT [5:0] DEC_MCOMMA_DETECT ALIGN_COMMA_WORD [1:0] Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 308 3. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. 4. Applies to MGTA only. 5. Applies to MGTB only. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 309 1. The default X depends on the operation. See Table C-28, page 320 for details. 2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 310 1. The default X depends on the operation. See Table C-28, page 320 for details. 2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 311 2. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. 3. TXSLEWRATE is set to 0 by default. It must be set to 1 for all serial rates below 6.25 Gb/s. The RocketIO Wizard sets this attribute to 1. Virtex-4 RocketIO MGT User Guide www.xilinx.com...
  • Page 312 3. This register value must equal the register value at address 0x49, bit[14:11] on MGTB. The attribute RXOUTDIV2SEL sets both registers upon configuration, but must be written to separately using the DRP. 4. Applies to MGTA only. 5. Applies to MGTB only. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 313 3. RXSELDACFIX[3:0] on MGTB is composed of bits [14:11] at address 0x62 in this table. 4. RXSELDACTRAN[4:0] on MGTB is composed of bits [10:6] at address 0x62 in this table. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 314 Table C-22: Dynamic Reconfiguration Port Memory Map: MGTB Address 63–67 Address CLK_COR_SEQ_2_2 CLK_COR_SEQ_1_2 CHAN_BOND_SEQ_2_2 CHAN_BOND_SEQ_1_2 [4:0] [4:0] [4:0] [4:0] UNUSED [15:0] CLK_COR_SEQ_1_1 CLK_COR_SEQ_2_1 CHAN_BOND_SEQ_2_1 CHAN_BOND_SEQ_1_1 [10:0] [10:0] [10:0] [10:0] www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 315 [10:5] [10:5] BYPASS_FDET [4:0] RXLOOPCAL_WAIT [1:0] Notes: 1. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 316 CHAN_BOND_SEQ_1_2 [10:5] [10:5] VCO_CTRL_ENABLE CYCLE_LIMIT_SEL [1:0] Notes: 1. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 317 “Receive Equalization” in Chapter 4 for details. Note that in a UCF file RXAFEEQ must be specified as a 9-bit value. The RXAFEEQ[8:3] bits are unused and can be set to 0. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 318 [5:0] BYPASS_FDET LOOPCAL_WAIT [1:0] CHAN_BOND_SEQ_1_3[10] RXLB Notes: 1. This attribute should never be changed from the default setting. Otherwise the MGT can operate below optimum levels, compromising overall performance. www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 319 TXDATA_SEL [13:12] RESERVED CHAN_BOND_SEQ_LEN [7:0] RESERVED [2:0] CHAN_BOND_SEQ_2_USE CHAN_BOND_ONE_SHOT CLK_COR_MIN_LAT UNUSED [5:0] [15:0] UNUSED CHAN_BOND_MODE [1:0] [1:0] CCCB_ARBITRATOR_DISABLE RESERVED OPPOSITE_SELECT PCS_BIT_SLIP POWER_ENABLE CHAN_BOND_LIMIT [5:0] DIGRX_SYNC_MODE RESERVED DIGRX_FWDCLK [2:0] [1:0] Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 320 2.488 155.42 0100 0100/0001 1GE, SRIO1 1.25 0110/1010 0011/0001 PCIe, SRIO2 0110 0010 XAUI GE, XAUI FC, 3.125 – 3.125 – 156.25 – 0110 0010 SRIO3 3.1875 3.1875 159.375 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 321: Appendix D: Special Analog Functions

    11111 00001 –43.750 11110 00010 –40.625 11101 00011 –37.500 11100 00100 –34.375 11011 00101 –31.250 11010 00110 –28.125 11001 00111 –25.000 11000 01000 –21.875 10111 01001 –18.750 10110 01010 Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 322 01010 10110 +21.875 01001 10111 +25.000 01000 11000 +28.125 00111 11001 +31.250 00110 11010 +34.375 00101 11011 +37.500 00100 11100 +40.625 00011 11101 +43.750 00010 11110 +46.875 00001 11111 www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 323 Receiver Sample Phase Adjustment Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 324 Appendix D: Special Analog Functions www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...

  • Page 325: Introduction

    Introduction This appendix describes important differences regarding migration from the Virtex®-II Pro/Virtex-II Pro X to the Virtex-4 RocketIO™ Multi-Gigabit Transceivers (MGTs). This appendix does not describe all of the features and capabilities of these devices, but only highlights relevant PCB, power supply, and reference clock differences.

  • Page 326: Clocking

    Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO Transceiver Design Migration Clocking As with Virtex-II Pro/Virtex-II Pro X MGTs, there are several available clock inputs. Table E-2 shows the clocks for each family and the serial speeds they are available for.

  • Page 327: Serial Rate Support

    Virtex-II Pro X devices allow dynamic changing of PMA attributes via the PMA attribute bus. Virtex-4 devices allow all attribute changes from the Dynamic Reconfiguration Port, plus any default values can be set in the HDL itself. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 328: Board Guidelines

    Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO Transceiver Design Migration Board Guidelines Power Supply Filtering For the Virtex-4 RocketIO transceiver, the voltage level of the power pins has been reduced to 1.2V in the case of the AVCCAUXRX and AVCCAUXTX. See Table E-5 Figure E-2.

  • Page 329: Other Minor Differences

    MGT column. These new package pins are RTERM and MGTVREF (see Chapter 6, “Analog and Board Design Considerations” more details). Table E-6 shows the termination options for each generation. Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

  • Page 330: Crc

    Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO Transceiver Design Migration Table E-6: Termination Options Termination Virtex-II Pro Virtex-II Pro X Virtex-4 Value 50/75Ω 50Ω 50Ω Voltage Pins CRC support has changed over the three generations of transceivers. Table E-7 shows the CRC support for all three transceiver families.

  • Page 331: Rxstatus Bus

    TXPRE_TAP_PD TXSLEWRATE Controls TX pre-emphasis and edge rate TX_PREMPHASIS TXEMPHLEVEL TXPOST_PRDRV_DAC TXDAT_PRDRV_DAC TXPOST_TAP_PD TXPRE_TAP_DAC Controls differential amplitude of the TX_DIFF_CTRL TXDOWNLEVEL TXPOST_TAP_DAC transmitted signal TXDAT_TAP_DAC Active equalization RXFER RXAFEEQ Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 332 Appendix E: Virtex-II Pro/Virtex-II Pro X to Virtex-4 RocketIO Transceiver Design Migration www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 333 Home The Characterization Report section is down toward the end of this page. Xilinx Site Registration and acceptance of a Design License Agreement are required in order to gain access to this document. Johnson, Howard. Signal Integrity Techniques and Loss Budgeting for RocketIO Transceivers.
  • Page 334 Appendix F: References www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 335 Analog and Board Design Considerations RX_CLOCK_DIVIDER TXPD RXAFEEQ TXPHASESEL Append/Remove Idle Clock Correction RXASYNCDIVIDE TXPLLNDIVSEL Attributes RXBY_32 TXPOST_TAP_DAC ALIGN_COMMA_WORD RXCDRLOS TXPOST_TAP_PD CCCB_ARBITRATOR_DISABLE RXCLK0_FORCE_PMACLK TXPRE_TAP_DAC CHAN_BOND_LIMIT RXCLKMODE TXPRE_TAP_PD CHAN_BOND_MODE RXCMADJ TXSLEWRATE CHAN_BOND_ONE_SHOT RXCPSEL TXTERMTRIM Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 336 Design Migration ble) Introduction Channel Bonding Primary Differences CLK_COR_SEQ_1_MASK, CLK_COR_SEQ_2_MASK, K-characters, valid (table) Virtex-II Pro to Virtex-II Pro X FPGA CLK_COR_SEQ_LEN Clock and Data Recovery Determining Correct CLK_COR_MIN_LAT Clock Correction www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 337 MGT Transmit Clocking (figure) RXRECCLK1 COMBUSOUT MGT, term definition RXRECCLK2 DADDR Microstrip Edge-Coupled Differential Pair (figure) RXRESET DCLK RXRUNDISP Microstrip/Stripline Bends RXSIGDET Migration Differences RXSLIDE Model Considerations RXSTATUS DRDY RXUSRCLK RXUSRCLK2 ENCHANSYNC Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...
  • Page 338 (LT1963A) Regulator (figure) teristics (table) RXRECCLK1 Power Supply Filtering RocketIO TXUSRCLK Switching Charac- RXRECCLK2 teristics (table) Powering RocketIO MGTs RXUSRCLK RocketIO Wizard Filtering RXUSRCLK2 Routing Serial Traces Regulators TXCRCCLK www.xilinx.com Virtex-4 RocketIO MGT User Guide UG076 (v4.1) November 2, 2008...
  • Page 339 Summary of Guidelines Symbol Alignment see Comma Detection User Guide Conventions Comma Definition Port and Attribute Names User Guide Organization Termination Termination (power) Time Domain Reflectometry (TDR) Timing Diagram Virtex-4 RocketIO MGT User Guide www.xilinx.com UG076 (v4.1) November 2, 2008...

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